Datasheet

ManualsBrandsSeeed Studio ManualsDevelopment Boards & KitsSTM32MP157C System on Module

D D

C C

B B

A A

Initial Release

Seeed SoM - STM32MP157C_v1.0_SCH_190521

DESCRIPTION

eMMC

PMU

DDR3

MPU_2

DATE

Title/Revision History

Revision History

SHEET NAME

REVISION

SHEET

Schematic: Seeed SoM - STM32MP157C

2019/05/21

MPU_1

07 PINOUT/LED

2019/09/04 Seeed SoM - STM32MP157C_v1.01_SCH_190904

2019/12/13 Seeed SoM - STM32MP157C_v1.01_SCH_191213 Change R5,R6 from 1k to 2k

Title:

Size: Document Number: Rev:

Date: Sheet: ofDraw By:

https://www.seeedstudio.com

v1.01A3

1 7Friday, December 13, 2019weifeng

Seeed SoM - STM32MP157C

01 Title / Revision History

Title:

Size: Document Number: Rev:

Date: Sheet: ofDraw By:

https://www.seeedstudio.com

v1.01A3

1 7Friday, December 13, 2019weifeng

Seeed SoM - STM32MP157C

01 Title / Revision History

Title:

Size: Document Number: Rev:

Date: Sheet: ofDraw By:

https://www.seeedstudio.com

v1.01A3

1 7Friday, December 13, 2019weifeng

Seeed SoM - STM32MP157C

01 Title / Revision History

Summary of content (7 pages)

PAGE 1
5 4 3 Schematic: Seeed SoM - STM32MP157C D SHEET SHEET NAME 2 1 Revision History DATE REVISION DESCRIPTION 01 Title/Revision History 2019/05/21 Seeed SoM - STM32MP157C_v1.0_SCH_190521 02 MPU_1 2019/09/04 Seeed SoM - STM32MP157C_v1.01_SCH_190904 03 MPU_2 2019/12/13 Seeed SoM - STM32MP157C_v1.01_SCH_191213 04 DDR3 05 eMMC 06 PMU 07 PINOUT/LED D Initial Release Change R5,R6 from 1k to 2k C C B B A A https://www.seeedstudio.
PAGE 2
5 4 3 2 1 D D [7] [7] ETH_RXD2 [7] ETH_RXD3 [7] QSPI_CLK [5] MMC2_DAT2 [5] MMC2_DAT3 [7] FDCAN2_RX [7] HDMI_CEC [7] DVP_VSYNC [7] LTDC_B6 [7] DVP_D7 [7] I2S2_CK [7] ETH_TX_EN [7] I2S2_WS [7] FDCAN2_TX OTG_VBUS [5] MMC2_DAT0 [5] MMC2_DAT1 C AB3 AA4 AC3 U2 V4 V3 AC8 AB8 A13 A8 Y17 AA18 AB19 N2 T2 C19 [6,7] PA0_W KUP [7] ETH_RX_CLK [7] ETH_MDIO [7] LTDC_B5 [7] DVP_HSYNC [7] LTDC_R4 [7] DVP_PCLK [7] ETH_RX_DV [5] MMC2_DAT4 [5] MMC2_DAT5 [7] HDMI_NRST [7] OTG_FS_DM [7] OTG_FS_DP [7] MOC1 [7] MOC2 DSI_
PAGE 3
5 4 3 2 1 D D VDD_CORE C28 1uF 10V,X5R C0402 E22 F22 H21 E21 J21 J22 H22 G21 G22 G23 H23 [4] DDR_D0 [4] DDR_D1 [4] DDR_D2 [4] DDR_D3 [4] DDR_D4 [4] DDR_D5 [4] DDR_D6 [4] DDR_D7 [4] DDR_DQS0 [4] DDR_DQSN0 [4] DDR_DQM0 C T21 U21 T22 W21 W23 T23 W22 Y21 U22 U23 V22 [4] DDR_D8 [4] DDR_D9 [4] DDR_D10 [4] DDR_D11 [4] DDR_D12 [4] DDR_D13 [4] DDR_D14 [4] DDR_D15 [4] DDR_DQS1 [4] DDR_DQSN1 [4] DDR_DQM1 B22 D22 D23 B21 A21 E23 D21 A22 C22 B23 C23 Y23 Y22 AB21 AB20 AC22 AC21 AA23 AA22 AB22 AB23 AA20 B
PAGE 4
5 4 VTT_DDR D 3 2 1 VDDQ_DDR D [3] [3] DDR_DQS0 DDR_DQSN0 [3] [3] DDR_DQS1 DDR_DQSN1 [3] [3] E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 DDR_D9 DDR_D11 DDR_D8 DDR_D15 DDR_D13 DDR_D12 DDR_D10 DDR_D14 DDR_D6 DDR_D1 DDR_D5 DDR_D3 DDR_D2 DDR_D0 DDR_D4 DDR_D7 C7 B7 F3 G3 D3 E7 DDR_DQM0 DDR_DQM1 VDDQ_DDR A1 A8 C1 C9 D2 E9 F1 H2 H9 J1 J9 L1 L9 B VREF_DDR M8 H1 C53 100nF 16V,X7R C0402 C54 100nF 16V,X7R C0402 RESET# CK CKn CKE CSn RASn CASn WEn A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
PAGE 5
4 3 2 1 VDD D D VDD R0402 R136 R137 R138 R139 R140 R141 R142 R143 R144 R145 R146 3V3 K6 N6 E5 N9 N8 N7 J12 P14 N3 P10 N1 M14 M13 M12 M11 M10 M9 M8 M7 P11 P12 P13 M3 M2 M1 L14 L13 L12 A10 A11 A12 A13 A14 B1 B7 G1 L3 L2 L1 K14 K13 K12 C179 10pF 50V,NPO C0402 DNP Layout Note: Place R134 C179 Close To MPU.
PAGE 6
5 4 D 3 1 D 5V_VIN 8 6 C186 10uF C0603 10V,X5R Layout Note: 12 5V_VIN 3A 10 C187 10uF C0603 10V,X5R 28 30 C188 10uF C0603 10V,X5R 24 R149 R0402 C 0R 5% BST_OUT Layout Note: BST_OUT 1A VDD 5V_VIN 3V3 C189 10uF C0603 10V,X5R 26 L8 1uH L2016 2.05A W PN201610H1R0MT C190 10uF C0603 10V,X5R 33 R150 R0402 37 0R 5% 32 15 VDDQ_DDR 13 VDD C191 10uF C0603 10V,X5R 22 C192 1uF C0402 10V,X5R 19 C193 1uF C0402 10V,X5R R152 4.
PAGE 7
5 D C Half-Duplex Master [2] I2S2_CK [2] I2S2_WS [2] I2S2_SDO [2] HDMI_CEC [2] HDMI_INT [2] HDMI_NRST [2] LTDC_B7 [2] LTDC_B6 [2] LTDC_B5 [2] LTDC_B4 [2] LTDC_B3 [2] LTDC_B2 [2] LTDC_B1 [2] LTDC_B0 [2] LTDC_G7 [2] LTDC_G6 [2] LTDC_G5 [2] LTDC_G4 [2] LTDC_G3 [2] LTDC_G2 [2] LTDC_G1 [2] LTDC_G0 [2] LTDC_R7 [2] LTDC_R6 [2] LTDC_R5 [2] LTDC_R4 [2] LTDC_R3 [2] LTDC_R2 [2] LTDC_R1 [2] LTDC_R0 [2] LTDC_CLK [2] LTDC_DE [2] LTDC_HSYNC [2] LTDC_VSYNC Layout Note: The LTCD signals must be length-matched 4 73 1 3