Datasheet

SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
r
t
BUF
7
LDC1612
,
LDC1614
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SNOSCY9A DECEMBER 2014REVISED MARCH 2018
Product Folder Links: LDC1612 LDC1614
Submit Documentation FeedbackCopyright © 2014–2018, Texas Instruments Incorporated
Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for T
A
= 25°C, V
DD
= 3.3 V. See
(1)
PARAMETER TEST CONDITIONS
(2)
MIN
(3)
TYP
(4)
MAX
(3)
UNIT
ƒ
INTCLK
Internal Reference Clock
Frequency range
35 43.4 55 MHz
T
Cf_int_μ
Internal Reference Clock
Temperature Coefficient mean
-13 ppm/°C
TIMING CHARACTERISTICS
t
WAKEUP
Wake-up Time from SD high-low
transition to I2C readback
2 ms
t
WD-TIMEOUT
Sensor recovery time (after
watchdog timeout)
5.2 ms
(1) This parameter is specified by design and/or characterization and is not tested in production.
6.6 Switching Characteristics - I2C
Unless otherwise specified, all limits ensured for T
A
= 25°C, VDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE LEVELS
V
IH
Input High Voltage 0.7ˣV
DD
V
V
IL
Input Low Voltage 0.3ˣV
DD
V
V
OL
Output Low Voltage (3mA sink
current)
0.4 V
HYS Hysteresis 0.1ˣV
DD
V
I2C TIMING CHARACTERISTICS
ƒ
SCL
Clock Frequency 10 400 kHz
t
LOW
Clock Low Time 1.3 μs
t
HIGH
Clock High Time 0.6 μs
t
HD;STA
Hold Time (repeated) START
condition
After this period, the first clock
pulse is generated
0.6 μs
t
SU;STA
Set-up time for a repeated START
condition
0.6 μs
t
HD;DAT
Data hold time 0 μs
t
SU;DAT
Data setup time 100 ns
t
SU;STO
Set-up time for STOP condition 0.6 μs
t
BUF
Bus free time between a STOP
and START condition
1.3 μs
t
VD;DAT
Data valid time 0.9 μs
t
VD;ACK
Data valid acknowledge time 0.9 μs
t
SP
Pulse width of spikes that must be
suppressed by the input filter
(1)
50 ns
Figure 1. I2C Timing