Datasheet

51
LDC1612 , LDC1614
www.ti.com SNOSCY9A –DECEMBER 2014–REVISED MARCH 2018
Product Folder Links: LDC1612 LDC1614
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Typical Application (continued)
h. The combined value for the CONFIG register (address 0x1A) is 0x1601.
We then read the conversion results for channel 0 and channel 1 every 1.00 ms from register addresses
0x00 to 0x03.
8.2.5 Recommended Initial Register Configuration Values
Based on the example configuration in section Detailed Design Procedure, the following register write sequence
is recommended:
Table 47. Recommended Initial Register Configuration Values (Single-Channel Operation)
ADDRESS VALUE REGISTER NAME COMMENTS
0x08 0x04D6 RCOUNT0 Reference count calculated from timing requirements (1 kSPS) and
resolution requirements
0x10 0x000A SETTLECOUNT0 Minimum settling time for chosen sensor
0x14 0x1002 CLOCK_DIVIDERS0 FIN_DIVIDER0 = 1, FREF_DIVIDER0 = 2
0x19 0x0000 ERROR_CONFIG Can be changed from default to report status and error conditions
0x1B 0x020C MUX_CONFIG Enable Channel 0 in continuous mode, set Input deglitch bandwidth to
3.3MHz
0x1E 0x9000 DRIVE_CURRENT0 Sets sensor drive current on channel 0
0x1A 0x1601 CONFIG Select active channel = ch 0, disable auto-amplitude correction and auto-
calibration, enable full current drive during sensor activation, select
external clock source, wake up device to start conversion. This register
write must occur last because device configuration is not permitted while
the LDC is in active mode.
Table 48. Recommended Initial Register Configuration Values (Multi-Channel Operation)
ADDRESS VALUE REGISTER NAME COMMENTS
0x08 0x04D6 RCOUNT0 Reference count calculated from timing requirements (1
kSPS) and resolution requirements
0x09 0x04D6 RCOUNT1 Reference count calculated from timing requirements (1
kSPS) and resolution requirements
0x10 0x000A SETTLECOUNT0 Minimum settling time for chosen sensor
0x11 0x000A SETTLECOUNT1 Minimum settling time for chosen sensor
0x14 0x1002 CLOCK_DIVIDERS0 FIN_DIVIDER0 = 1, FREF_DIVIDER0 = 2
0x15 0x1002 CLOCK_DIVIDERS_1 FIN_DIVIDER1 = 1, FREF_DIVIDER1 = 2
0x19 0x0000 ERROR_CONFIG Can be changed from default to report status and error
conditions
0x1B 0x820C MUX_CONFIG Enable Ch 0 and Ch 1 (sequential mode), set Input deglitch
bandwidth to 3.3MHz
0x1E 0x9000 DRIVE_CURRENT0 Sets sensor drive current on ch 0
0x1F 0x9000 DRIVE_CURRENT1 Sets sensor drive current on ch 1
0x1A 0x1601 CONFIG Disable auto-amplitude correction and auto-calibration,
enable full current drive during sensor activation, select
external clock source, wake up device to start conversion.
This register write must occur last because device
configuration is not permitted while the LDC is in active
mode.