Datasheet
46
LDC1612
,
LDC1614
SNOSCY9A –DECEMBER 2014–REVISED MARCH 2018
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(1) Channels 2 and 3 are only available for LDC1614
(2) If ƒ
SENSOR
≥ 8.75 MHz, then FIN_DIVIDERx must be ≥ 2
Table 43. Clock Frequency Requirements
MODE
(1)
REFERENCE
SOURCE
VALID ƒ
REFx
RANGE
VALID ƒ
INx
RANGE
SET
FIN_DIVIDERx to
VALID
SETTLECOUNTx
SETTINGS
VALID RCOUNTx
SETTINGS
Multi-Channel Internal ƒ
REFx
≤ 55 MHz
< ƒ
REFx
/4 ≥ b0001
(2)
> 3 > 8
External ƒ
REFx
≤ 40 MHz
Single-Channel Either external or
internal
ƒ
REFx
≤ 35 MHz
(1) Channels 2 and 3 are only available for LDC1614
Table 44 shows the clock configuration registers. Each input channel has a dedicated configuration which can be
set independently.
Table 44. Clock Configuration Registers
CHANNEL
(1)
CLOCK REGISTER FIELD VALUE
All
ƒ
CLK
= Reference
Clock Source
CONFIG, addr 0x1A REF_CLK_SRC [9] b0 = internal oscillator is used as the
reference clock
b1 = external clock source is used as the
reference clock
0
ƒ
REF0
CLOCK_DIVIDERS0,
addr 0x14
FREF_DIVIDER0 [9:0] ƒ
REF0
= ƒ
CLK
/ FREF_DIVIDER0
1
ƒ
REF1
CLOCK_DIVIDERS1,
addr 0x15
FREF_DIVIDER1 [9:0] ƒ
REF1
= ƒ
CLK
/ FREF_DIVIDER1
2
ƒ
REF2
CLOCK_DIVIDERS2,
addr 0x16
FREF_DIVIDER2 [9:0] ƒ
REF2
= ƒ
CLK
/ FREF_DIVIDER2
3
ƒ
REF3
CLOCK_DIVIDERS3,
addr 0x17
FREF_DIVIDER3 [9:0] ƒ
REF3
= ƒ
CLK
/ FREF_DIVIDER3
0
ƒ
IN0
CLOCK_DIVIDERS0,
addr 0x14
FIN_DIVIDER0 [15:12] ƒ
IN0
= ƒ
SENSOR0
/ FIN_DIVIDER0
1
ƒ
IN1
CLOCK_DIVIDERS1,
addr 0x15
FIN_DIVIDER1 [15:12] ƒ
IN1
= ƒ
SENSOR1
/ FIN_DIVIDER1
2
ƒ
IN2
CLOCK_DIVIDERS2,
addr 0x16
FIN_DIVIDER2 [15:12] ƒ
IN2
= ƒ
SENSOR2
/ FIN_DIVIDER2
3
ƒ
IN3
CLOCK_DIVIDERS3,
addr 0x17
FIN_DIVIDER3 [15:12] ƒ
IN3
= ƒ
SENSOR3
/ FIN_DIVIDER3
(1) Channels 2 and 3 are available for LDC1614 only.
8.1.7 Input Deglitch Filter
The input deglitch filter suppresses EMI and ringing above the sensor frequency. It does not impact the
conversion result as long as its bandwidth is configured to be above the maximum sensor frequency. The input
deglitch filter can be configured in MUX_CONFIG.DEGLITCH register field as shown in Table 45 . This setting
applies to all channels. For optimal performance, it is recommended to select the lowest setting that exceeds the
highest sensor oscillation frequency for all selected channels. For example, if the maximum sensor frequency is
2.8 MHz, choose MUX_CONFIG.DEGLITCH = b100 (3.3 MHz).
Table 45. Input Deglitch Filter Register
CHANNEL
(1)
MUX_CONFIG.DEGLITCH REGISTER VALUE DEGLITCH FREQUENCY
ALL b001 1.0 MHz
ALL b100 3.3 MHz
ALL b101 10 MHz
ALL b011 33 MHz