Datasheet

SCL
SDA
START
AVOID SDA PULSE
AFTER START
ADDR
14
LDC1612 , LDC1614
SNOSCY9A –DECEMBER 2014–REVISED MARCH 2018 www.ti.com
Product Folder Links: LDC1612 LDC1614
Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated
Programming (continued)
7.5.2 Pulses on I2C
The I2C interface of the LDC is designed to operate with the standard I2C transactions detailed in the I2C
specification; however it is not suitable for use in an I2C system which supports early termination of transactions.
A STOP condition or other early termination occurring before the normal end of a transaction (ACK) is not
supported and may corrupt that transaction and/or the following transaction. The device is also sensitive to any
(extraneous) pulse on SDA during the SCL low period of the first bit position of the i2c_address byte. To ensure
proper LDC operation, the master device should not transmit this type of waveform. An example of an
unsupported I2C waveform is shown in Figure 13. Any such pulses should not have a duration which exceeds
the device t
SP
specification.
Figure 13. Example of SDA Pulse Between I2C START and ADDR Which Must be Avoided by the I2C
Master
7.5.3 Multi Register Data Readback
The LDC1612/LDC1614 conversion data spans 2 registers. To avoid multi-conversion data corruption, the device
uses an internal shadow register to hold conversion results for each channel. When a conversion completes, the
corresponding internal shadow register is updated with the new conversion result. When the DATAx_MSB
register is read, the contents of both the DATAx_MSB and DATAx_LSB registers are updated with the new
conversion data.
Therefore, to correctly retrieve the conversion results for a given channel, the proper sequence is to first read the
DATAx_MSB register, and then read the DATAx_LSB register.