Datasheet
1 9
Ack by
Slave
Start by
Master
SCL
SDA
Frame 1
Serial Bus Address Byte
from Master
R/W
A2 A0A1A3A4A5A6
D7 D6 D5 D4 D3 D2 D1 D0
1 9
Nack by
Master
Stop by
Master
1 9
D15 D14 D13 D12 D11 D10 D9 D8
Ack by
Master
Frame 4
Data MSB from
Slave
Frame 5
Data LSB from
Slave
1 9
R7 R6 R5 R4 R3 R2 R1 R0
Ack by
Slave
Frame 2
Slave Register
Address
1 9
Start by
Master
SCL
SDA
Frame 3
Serial Bus Address Byte
from Master
R/W
A2
A0A1
A3A4A5A6
Ack by
Slave
1 9
Ack by
Slave
Start by
Master
SCL
SDA
Frame 1
Serial Bus Address Byte
from Master
R/W
A2 A0A1A3A4A5A6
D7 D6 D5 D4 D3 D2 D1 D0
1 9
Ack by
Slave
Stop by
Master
1 9
D15 D14 D13 D12 D11 D10 D9 D8
Ack by
Slave
Frame 3
Data MSB from
Master
Frame 4
Data LSB from
Master
1 9
R7 R6 R5 R4 R3 R2 R1 R0
Ack by
Slave
Frame 2
Slave Register
Address
SCL
SDA
13
LDC1612
,
LDC1614
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SNOSCY9A –DECEMBER 2014–REVISED MARCH 2018
Product Folder Links: LDC1612 LDC1614
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7.5 Programming
The LDC1612/4 device uses an I2C interface to access control and data registers. The recommended
configuration procedure is to put the device into Sleep Mode, set the appropriate registers, and then enter
Normal Mode. Conversion results must be read while the device is in Normal Mode. Setting the device into
Shutdown mode will reset the device configuration.
7.5.1 I2C Interface Specifications
The LDC1612/4 use I2C for register access with a maximum speed of 400 kbit/s. The device registers are 16 bits
wide, and so a repeated start is used to access the 2
nd
byte of data. This sequence follows the standard I2C 7bit
slave address followed by an 8 bit pointer register byte to set the register address. Refer to Figure 11 and
Figure 12 for proper protocol diagrams. The device does not use I2C clock stretching.
When the ADDR pin is set low, the device I2C address is 0x2A; when the ADDR pin is set high, the I2C address
is 0x2B. The ADDR pin setting can be changed while the device is in Shutdown Mode to select the alternate I2C
address.
Figure 11. I2C Write Register Sequence
Figure 12. I2C Read Register Sequence