Datasheet

MCP9600
DS20005426C-page 16  2015-2017 Microchip Technology Inc.
4.1.5 DATA VALID
After the Start condition, each bit of data in transmis-
sion needs to be settled for a time specified by t
SU-DATA
before SCL toggles from low-to-high (see the “Sensor
Serial Interface Timing Specifications” section).
4.1.6 ACKNOWLEDGE (ACK/NAK)
Each receiving device, when addressed, is expected to
generate an ACK bit after the reception of each byte.
The master device must generate an extra clock pulse
for ACK to be recognized.
The Acknowledging device pulls down the SDA line for
t
SU-DATA
before the low-to-high transition of SCL from
the master. SDA also needs to remain pulled down for
t
HD-DAT
after a high-to-low transition of SCL.
During read, the master must signal an End-of-Data
(EOD) to the slave by not generating an ACK bit (NAK)
once the last bit has been clocked out of the slave. In
this case, the slave will leave the data line released to
enable the master to generate the Stop condition.
4.1.7 CLOCK STRETCHING
During the I
2
C read operation, this device will hold the
I
2
C clock line low for t
STRECH
after the falling edge of
the ACK signal. In order to prevent bus contention, the
master controller must release or hold the SCL line low
during this period.
In addition, the master controller must provide eight
consecutive clock cycles after generating the ACK bit
from a read command. This allows the device to push
out data from the SDA Output Shift registers. Missing
clock cycles could result in bus contention. At the end
of the data transmission, the master controller must
provide the NAK bit, followed by a Stop bit to terminate
communication.
FIGURE 4-2: Clock Stretching.
4.1.8 SEQUENTIAL READ
During a sequential read, the device transmits data
from the proceeding register, starting from the previ-
ously set Register Pointer. The MCP9600 maintains an
Internal Address Pointer, which is incremented at the
completion of each read data transmission, followed by
an ACK from the master. A Stop bit terminates the
sequential read.
A
C
K
xxxx
A
C
K
A
0
78 12345678
x
R
MCP9600
Master
xxx
MCP9600 Clock Stretching – t
STRETCH
T
H
MSB Data