Datasheet

[AK09918]
016014242-E-00 2016/11
- 7 -
8.4. I
2
C Bus Interface
I
2
C bus interface is compliant with Standard mode and Fast mode. Standard/Fast mode is selected
automatically by fSCL.
 Standard mode
fSCL ≤ 100kHz
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSCL
SCL clock frequency
100
kHz
tHIGH
SCL clock “High” time
4.0

s
tLOW
SCL clock “Low” time
4.7

s
tR
SDA and SCL rise time
1.0

s
tF
SDA and SCL fall time
0.3

s
tHD:STA
Start Condition hold time
4.0

s
tSU:STA
Start Condition setup time
4.7

s
tHD:DAT
SDA hold time (vs. SCL falling edge)
0

s
tSU:DAT
SDA setup time (vs. SCL rising edge)
250
ns
tSU:STO
Stop Condition setup time
4.0

s
tBUF
Bus free time
4.7

s
 Fast mode
100kHz ≤ fSCL ≤ 400kHz
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSCL
SCL clock frequency
400
kHz
tHIGH
SCL clock “High” time
0.6

s
tLOW
SCL clock “Low” time
1.3

s
tR
SDA and SCL rise time
0.3

s
tF
SDA and SCL fall time
0.3

s
tHD:STA
Start Condition hold time
0.6

s
tSU:STA
Start Condition setup time
0.6

s
tHD:DAT
SDA hold time (vs. SCL falling edge)
0

s
tSU:DAT
SDA setup time (vs. SCL rising edge)
100
ns
tSU:STO
Stop Condition setup time
0.6

s
tBUF
Bus free time
1.3

s
tSP
Noise suppression pulse width
50
ns
[I
2
C bus interface timing]
tHIGH
SCL
SDA
VIH
tLOW
tBUF
tHD:STA
tR
tF
tHD:DAT
tSU:DAT
tSU:STA
Stop
Start
Start
Stop
tSU:STO
VIL
VIH
VIL
tSP
SCL
VIH
VIL
1/fSCL