Datasheet

Bosch Sensortec

| BMI088 Data sheet

37 |

Modifications reserved | Data subject to change without notice

Document number: BST-BMI088-DS001-1

Revision_1.3_05201

The I²C protocol works as follows:

START: Data transmission on the bus begins with a high to low transition on the SDA line while SCL is

held high (start condition (S) indicated by I²C bus master). Once the START signal is transferred by the

master, the bus is considered busy.

STOP: Each data transfer should be terminated by a Stop signal (P) generated by master. The STOP

condition is a low to HIGH transition on SDA line while SCL is held high.

ACK: Each byte of data transferred must be acknowledged. It is indicated by an acknowledge bit sent

by the receiver. The transmitter must release the SDA line (no pull down) during the acknowledge pulse

while the receiver must then pull the SDA line low so that it remains stable low during the high period of

the acknowledge clock cycle.

In the following diagrams, these abbreviations are used:

S Start

P Stop

ACKS Acknowledge by slave

ACKM Acknowledge by master

NACKM Not acknowledge by master

RW Read / Write

A START immediately followed by a STOP (without SCL toggling from ´VDDIO´ to ´GND´) is not

supported. If such a combination occurs, the STOP is not recognized by the device.

I²C write access:

I²C write access can be used to write a data byte in one sequence.

The sequence begins with start condition generated by the master, followed by 7 bits slave address and

a write bit (RW = 0). The slave sends an acknowledge bit (ACK = 0) and releases the bus. Then the

master sends the one byte register address. The slave again acknowledges the transmission and waits

for the 8 bits of data, which shall be written to the specified register address. After the slave

acknowledges the data byte, the master generates a stop signal and terminates the writing protocol.

Example of an I²C write access to the accelerometer, writing 0xA8 to address ox40 (i.e. setting

continuous filter function, averaging to 4 samples, ODR to 100Hz):

Figure 4: I²C write

Start

ACKS

dummy

ACKS

Stop

S 0 0 1 1 0 0 0 0 A 0 1 0 0 0 0 0 0 A 1 0 1 0 1 0 0 0 A P

Slave address (0x18)

Data (0xA8)