Datasheet

Data Sheet
BMA456
Page 5
BST-BMA456-DS000-01 | Version 1.1 | October 2017 Bosch Sensortec
© Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights. We reserve all rights of disposal such as copying and passing on to third parties.
BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are subject to change without notice.
Register (0x41) ACC_RANGE .................................................................................................. 80
Register (0x44) AUX_CONF ..................................................................................................... 81
Register (0x45) FIFO_DOWNS ................................................................................................ 81
Register (0x46) FIFO_WTM_0 .................................................................................................. 82
Register (0x47) FIFO_WTM_1 .................................................................................................. 83
Register (0x48) FIFO_CONFIG_0 ............................................................................................ 83
Register (0x49) FIFO_CONFIG_1 ............................................................................................ 84
Register (0x4B) AUX_DEV_ID .................................................................................................. 85
Register (0x4C) AUX_IF_CONF ............................................................................................... 85
Register (0x4D) AUX_RD_ADDR ............................................................................................. 86
Register (0x4E) AUX_WR_ADDR ............................................................................................. 86
Register (0x4F) AUX_WR_DATA .............................................................................................. 87
Register (0x53) INT1_IO_CTRL ............................................................................................... 87
Register (0x54) INT2_IO_CTRL ............................................................................................... 88
Register (0x55) INT_LATCH ..................................................................................................... 89
Register (0x56) INT1_MAP ....................................................................................................... 90
Register (0x57) INT2_MAP ....................................................................................................... 90
Register (0x58) INT_MAP_DATA .............................................................................................. 91
Register (0x59) INIT_CTRL ...................................................................................................... 91
Register (0x5E) FEATURES_IN................................................................................................ 92
Register (0x5F) INTERNAL_ERROR ........................................................................................ 96
Register (0x6A) NVM_CONF .................................................................................................... 96
Register (0x6B) IF_CONF ........................................................................................................ 97
Register (0x6D) ACC_SELF_TEST .......................................................................................... 97
Register (0x70) NV_CONF ....................................................................................................... 98
Register (0x71) OFFSET_0 ...................................................................................................... 99
Register (0x72) OFFSET_1 ...................................................................................................... 99
Register (0x73) OFFSET_2 .................................................................................................... 100
Register (0x7C) PWR_CONF ................................................................................................. 100
Register (0x7D) PWR_CTRL .................................................................................................. 101
Register (0x7E) CMD.............................................................................................................. 101
6. DIGITAL INTERFACES .............................................................................................................. 103
6.1. INTERFACES ..................................................................................................................... 103
6.2. PRIMARY INTERFACE ......................................................................................................... 104
6.3. PRIMARY INTERFACE I2C/SPI PROTOCOL SELECTION ......................................................... 105
6.4. SPI INTERFACE AND PROTOCOL ......................................................................................... 105
6.5. PRIMARY I2C INTERFACE ................................................................................................... 110
6.6. SPI AND I²C ACCESS RESTRICTIONS .................................................................................. 114
6.7. AUXILIARY INTERFACE ....................................................................................................... 114
7. PIN-OUT AND CONNECTION DIAGRAMS .............................................................................. 115
7.1. PIN-OUT ........................................................................................................................... 115
7.2. CONNECTION DIAGRAMS WITHOUT AUXILIARY INTERFACE .................................................... 116