Datasheet

Data Sheet
BMA456
Page 43
BST-BMA456-DS000-01 | Version 1.1 | October 2017 Bosch Sensortec
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Note: Specifications within this document are subject to change without notice.
4.7. General Interrupt Pin configuration
Electrical Interrupt Pin Behavior
Both interrupt pins INT1 and INT2 can be configured to show the desired electrical behavior.
Interrupt pins can be enabled in INT1_IO_CTRL.output_en respectively INT2_IO_CTRL.output_en.
The characteristic of the output driver of the interrupt pins may be configured with bits
INT1_IO_CTRL.od and INT2_IO_CTRL.od. By setting these bits to 0b1, the output driver shows open-
drive characteristic, by setting the configuration bits to 0b0, the output driver shows push-pull
characteristic.
The electrical behavior of the Interrupt pins, whenever an interrupt is triggered, can be configured as
either “active-high” or “active-low” via INT1_IO_CTRL.lvl respectively INT2_IO_CTRL.lvl.
Both interrupt pins can be configured as input pins via INT1_IO_CTRL.input_en respectively
INT2_IO_CTRL.input_en. This is necessary when FIFO tag feature is used (see chapter 0). If both are
enabled, the input (e.g. marking FIFO) is driven by the interrupt output.
BMA456 supports edge and level triggered interrupt inputs, this can be configured through
INT1_IO_CTRL.edge_ctrl respectively INT2_IO_CTRL.edge_ctrl.
BMA456 supports non-latched and latched interrupts modes for data-ready, FIFO full and FIFO
watermark. The mode is selected by INT_LATCH.int_latch. The feature interrupts described in chapter
4.6 support only latched mode described below.
In latched mode an asserted interrupt status in INT_STATUS_0 or INT_STATUS_1 and the selected
pin are cleared if the corresponding status register is read. If more than one interrupt pin is used in
latched mode, all interrupts in INT_STATUS_0 should be mapped to one pin and all interrupts in
INT_STATUS_1 should be mapped to the other pin. If just one interrupt pin is used all interrupts may
be mapped to this pin. If the activation condition still holds when it is cleared, the interrupt status is
asserted again when the interrupt condition holds again.
In the non-latched mode (only for data-ready, FIFO full and FIFO watermark) the interrupt status bit
and the selected pin are reset as soon as the activation condition is not valid anymore.
Interrupt Pin Mapping
In order, for the Host to react to the features output, they can be mapped to the external PIN1 or PIN2,
by setting the corresponding bits from the registers INT1_MAP, respectively INT2_MAP.
To disconnect the features outputs to the external pins, the same corresponding bits must be reset,
from the registers, INT1_MAP, respectively INT2_MAP.
Once a feature triggered the output pin, the Host can read out the corresponding bit from the register,
INT_STATUS_0 (Feature Interrupts) or INT_STATUS_1 (FIFO and data ready).