Datasheet

Data Sheet
BMA456
Page 111
BST-BMA456-DS000-01 | Version 1.1 | October 2017 Bosch Sensortec
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Note: Specifications within this document are subject to change without notice.
The figure below shows the definition of the I²C timings given in Table 28:
I²C timing diagram
The I²C protocol works as follows:
START: Data transmission on the bus begins with a high to low transition on the SDA line while SCL
is held high (start condition (S) indicated by I²C bus master). Once the START signal is transferred by
the master, the bus is considered busy.
STOP: Each data transfer should be terminated by a Stop signal (P) generated by master. The STOP
condition is a low to high transition on SDA line while SCL is held high.
ACKS: Each byte of data transferred must be acknowledged. It is indicated by an acknowledge bit
sent by the receiver. The transmitter must release the SDA line (no pull down) during the acknowledge
pulse while the receiver must then pull the SDA line low so that it remains stable low during the high
period of the acknowledge clock cycle.
In the following diagrams these abbreviations are used:
S Start
P Stop
ACKS Acknowledge by slave
ACKM Acknowledge by master
NACKM Not acknowledge by master
RW Read / Write
A START immediately followed by a STOP (without SCL toggling from ´VDDIO´ to ´GND´) is not
supported. If such a combination occurs, the STOP is not recognized by the device.
t
HDDAT
t
f
t
BUF
SDA
SCL
SDA
t
LOW
t
HDSTA
t
r
t
SUSTA
t
HIGH
t
SUDAT
t
SUSTO