Datasheet

Data Sheet
BMA456
Page 105
BST-BMA456-DS000-01 | Version 1.1 | October 2017 Bosch Sensortec
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BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are subject to change without notice.
6.3. Primary Interface I2C/SPI Protocol Selection
The protocol is automatically selected based on the chip select CSB pin behavior after power-up.
At reset / power-up, BMA456 is in I2C mode. If CSB is connected to VDDIO during power-up and not
changed the sensor interface works in I2C mode. For using I2C, it is recommended to hard-wire the
CSB line to VDDIO. Since power-on-reset is only executed when, both VDD and VDDIO are
established, there is no risk of incorrect protocol detection due to power-up sequence.
If CSB sees a rising edge after power-up, the BMA456 interface switches to SPI until a reset or the
next power-up occurs. Therefore, a CSB rising edge is needed before starting the SPI communication.
Hence, it is recommended to perform a SPI single read of register CHIP_ID (the obtained value will
be invalid) before the actual communication start, in order to use the SPI interface.
If toggling of the CSB bit is not possible without data communication, there is in addition the spi_en bit
in Register NV_CONF, which can be used to permanently set the primary interface to SPI without the
need to toggle the CSB pin at every power-up or reset.
6.4. SPI interface and protocol
The timing specification for SPI of the BMA456 is given in the following table:
SPI timing, valid at V
DDIO
≥ 1.71V
Parameter
Symbol
Condition
Min
Max
Units
Clock Frequency
f
SPI
Max. Load on
SDI or SDO =
30pF, V
DDIO
≥
1.62 V
10
MHz
V
DDIO
< 1.62V
7
MHz
SCK Low Pulse
t
SCKL
V
DDIO
>=1.62V
45
ns
SCK High Pulse
t
SCKH
V
DDIO
>=1.62V
45
ns
SCK Low Pulse
t
SCKL
V
DDIO
<1.62V
66
ns
SCK High Pulse
t
SCKH
V
DDIO
<1.62V
66
ns
SDI Setup Time
t
SDI_setup
20
ns
SDI Hold Time
t
SDI_hold
20
ns
SDO Output Delay
t
SDO_OD
Load = 30pF,
V
DDIO
≥ 1.62V
30
ns
CSB Setup Time
t
CSB_setup
40
ns
CSB Hold Time
t
CSB_hold
40
ns
Idle time between
write accesses,
suspend mode, low-
power mode 1
t
IDLE_wacc_sum
1000
µs
Idle time after write
and read access,
active state
t
IDLE_wr_act
2
µs