Datasheet

Preliminary Data Sheet
BMA400
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BST-BMA400-DS000-00 | Version 0.1 | November 2017 Bosch Sensortec
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Note: Specifications within this document are subject to change without notice.
4.6. Interrupt Features
The following interrupts exist in the BMA400:
Basic interrupts
- Data ready interrupt
- FIFO watermark
- FIFO full
- Interrupt engine overrun
- Wake-up interrupt
Advanced Interrupts
- Generic interrupt 1
- Generic interrupt 2
- Step detector interrupt/step counter
- Activity changed interrupt
- Single tap / Double tap sensing
- Orientation changed interrupt
Basic interrupts can all be enabled independently from each other.
Advanced interrupts are only available in normal mode, the interrupt engine is disabled in low power
mode and sleep mode.
The interrupts served by the interrupt engine. They share the same resources and time-slices, thus,
enabling too many interrupts of this type in parallel lead to a so-called Interrupt engine overrun. This
interrupt indicating that the interrupt engine could not finish calculating all selected interrupt conditions.
If this occurs, advanced interrupts of lesser importance must be disabled until the Interrupt engine
overrun condition/interrupt vanishes.
Any change of an interrupt configuration must be executed when the corresponding interrupt is
disabled.
Most interrupts require a data rate of 100Hz, only tap sensing requires 200Hz. It is then necessary to
configure the data source of the tap sensing interrupt, filter acc_filt1, to 200Hz, which implies that the
other interrupts requiring 100Hz data rate use another filter.
Interrupt pin mapping, interrupt status
The BMA400 supports flexible INT1 and INT2 pin mapping configurations via interrupt mapping
registers INT1_MAP, INT2_MAP and INT12_MAP. Depending on these registers settings, all interrupt
sources are mapped to the INT1 and INT2 pins.
The status of the interrupts can be read out at the status registers INT_STAT0, INT_STAT1 and
INT_STAT2.
Additionally, the step counter value is stored in the registers STEP_CNT0…STEP_CNT3 . These
registers need to be read out using a burst read to avoid one register getting updated while another
step count register is read.
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