Datasheet
Preliminary Data Sheet
BMA400
Page 28 /
Confidential
BST-BMA400-DS000-00 | Version 0.1 | November 2017 Bosch Sensortec
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Note: Specifications within this document are subject to change without notice.
4.3. Sensor Data
Acceleration Data
The width of acceleration data is 12 bits given in two´s complement representation in the registers
0x04 to 0x09 (ACC_X_LSB, ACC_X_MSB, ACC_Y_LSB, ACC_Y_MSB, ACC_Z_LSB, ACC_Z_MSB ).
The 12 bits for each axis are split into an MSB upper part and an LSB lower part.
In order to ensure the integrity of the acceleration data read, the content of all data registers must be
read in a single burst read, since these registers are write-protected during a read access. As soon as
the burst read is finished the register content will be updated if new data are available.
Filter Configuration
Two major filter paths are implemented, see blockdiagram. Filter output can either be fed into the data
registers, into the FIFO, or used to process interrupts in the interrupt engine. This is selectable by
customer.
Filter1 (acc_filt1) has a data rate between 800Hz and 12.5Hz, controlled by ACC_CONFIG0.acc_odr.
Its bandwidth can be configured additionally by ACC_CONFIG0.filt1_bw:
ACC_CONFIG0.filt1_bw = 0x0 0.48 x ODR
ACC_CONFIG0.filt1_bw = 0x1 0.24 x ODR
ACC_CONFIG0.acc_odr <3:0>
Output Data Rate [Hz]
0xB .. 0xF
800
0xA
400
0x9
200
0x8
100
0x7
50
0x6
25
0x0 .. 0x5
12.5
Filter2 (acc_filt2) has a fixed data rate of 100 Hz.
In addition, these 100 Hz data is used by a third filter and filtered with a bandwidth of 1 Hz. The output
data rate will stay at 100 Hz. This data can be used as input for the data registers and also in the
interrupt engine. Access via FIFO is not possible.
ACC_CONFIG2.data_src_reg<1:0>
Filter output going into data registers (not FIFO!)
0x0,0x3
acc_filt1(selectable ODR)
0x01
acc_filt2 (100Hz ODR)
0x02
acc_filt_lp (1 Hz BW, 100 Hz ODR)
FIFO_CONFIG0.fifo_data_src
Filter output going into FIFO
0x0
acc_filt1(selectable ODR)
0x1
acc_filt2 (100Hz ODR)
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