Datasheet

Preliminary Data Sheet
BMA400
Page 131 /
Confidential
BST-BMA400-DS000-00 | Version 0.1 | November 2017 Bosch Sensortec
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Note: Specifications within this document are subject to change without notice.
I²C write access:
I²C write access can be used to write a data byte in one sequence.
The sequence begins with start condition generated by the master, followed by 7 bits slave address
and a write bit (RW = 0). The slave sends an acknowledge bit (ACKS = 0) and releases the bus. Then
the master sends the one byte register address. The slave again acknowledges the transmission and
waits for the 8 bits of data which shall be written to the specified register address. After the slave
acknowledges the data byte, the master generates a stop signal and terminates the writing protocol.
Example of an I²C write access:
Start R/W ACK ACK ACK
Stop
0 0 1 0 1 0 S 0 L 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1
Master -> Slave
S
Slave -> Master
L: tie to LOW, not part of address
defined by SDO
Slave Adress
Register data (0x01)
Register address (0x41)
I²C write
Multi-byte writes are supported without restriction on normal registers.
Start R/W ACK ACK ACK
0 0 1 0 1 0 S 0 L 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1
Master->Slave
ACK ACK
Stop
Slave->Master
L 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1
Slave Adress
Register data (0x01)
Register address (0x41)
Register address (0x42)
Register data (0x01)
I²C read access:
I²C read access also can be used to read one or multiple data bytes in one sequence.
A read sequence consists of a one-byte I²C write phase followed by the I²C read phase. The two parts
of the transmission must be separated by a repeated start condition (S). The I²C write phase addresses
the slave and sends the register address to be read. After slave acknowledges the transmission, the
master generates again a start condition and sends the slave address together with a read bit (RW =
1). Then the master releases the bus and waits for the data bytes to be read out from slave. After each
data byte the master has to generate an acknowledge bit (ACKS = 0) to enable further data transfer.
A NACKM (ACKS = 1) from the master stops the data being transferred from the slave. The slave
releases the bus so that the master can generate a STOP condition and terminate the transmission.
The register address is automatically incremented and, therefore, more than one byte can be
sequentially read out. Once a new data read transmission starts, the start address will be set to the
register address specified since the latest I²C write command. By default the start address is set at
0x00. In this way repetitive multi-bytes reads from the same starting address are possible.
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