Preliminary Data Sheet BMA400 Digital, triaxial acceleration sensor A D rN de ud D un de St ed tia la nd Se e rN io nd la tia en fid C on A un d ee C on Se fid en St tia ud la io nd un de rN D A Bosch Sensortec en Preliminary Data Sheet BMA400 0 273 141 xyz Document revision 0.1 Release date 03 November 2017 Document number BST-BMA400-DS000-00 Notes Specifications are preliminary and subject to change without notice.
Preliminary Data Sheet BMA400 Page 2 / Confidential BMA400 D A 12 bit, digital, triaxial acceleration sensor with smart on-chip motion and position-triggered interrupt features.
Preliminary Data Sheet BMA400 Page 3 / Confidential A Table of contents rN D Contents SPECIFICATION............................................................................................................................. 8 2. ABSOLUTE MAXIMUM RATINGS .............................................................................................. 10 3. QUICK START GUIDE ................................................................................................................. 11 de 1.
Preliminary Data Sheet BMA400 Page 4 / Confidential rN D A Interrupt pin mapping, interrupt status ...................................................................................... 43 Generic Interrupt 1 and 2 .......................................................................................................... 44 Step Detector / Step Counter .................................................................................................... 47 Activity changed interrupt ......................
Preliminary Data Sheet BMA400 Page 5 / Confidential A D rN de ud D un de St ed C on fid en tia la nd Se e rN io nd la tia en fid A un d ee Se on C C on fid en St tia ud la io nd un de rN D A Register (0x26) FIFO_CONFIG0 .............................................................................................. 79 Register (0x27) FIFO_CONFIG1 ..............................................................................................
Preliminary Data Sheet BMA400 Page 6 / Confidential A D rN de ud D un de St ed la nd Se e rN io nd la en fid on DIGITAL INTERFACES .............................................................................................................. 123 C INTERFACE ....................................................................................................................... 123 6.2. INTERFACE I2C/SPI PROTOCOL SELECTION ..............................................................
Preliminary Data Sheet BMA400 8. Page 7 / Confidential PACKAGE................................................................................................................................... 136 PACKAGE OUTLINE DIMENSIONS ......................................................................................... 136 8.2. SENSING AXIS ORIENTATION............................................................................................... 137 8.3. LANDING PATTERN RECOMMENDATION .....................
Preliminary Data Sheet BMA400 Page 8 / Confidential 1. Specification A Unless stated otherwise, the given values are over lifetime, operating temperature and voltage ranges. Minimum/maximum values are ±3. 1.8 de Power-Up Time ts_up Operating Temperature TA BST-BMA400-DS000-00 | Version 0.1 | November 2017 0.3VDDIO A rN nd 14 de St 200 nA tia en µA nA la Se e -40 D io 0.
Preliminary Data Sheet BMA400 Page 9 / Confidential A D A Hz rN Hz ud 25 %FS un µg/Hz la nd 220 de St ed Typ 2 tia en EA MECHANICAL CHARACTERISTICS Condition Min relative contribution between any two of the three axes relative to package outline fid Alignment Error 0.48*ODR 0.5 Max Units % ° C on Symbol S Hz 0.
Preliminary Data Sheet BMA400 Page 10 / Confidential 2. Absolute maximum ratings A Absolute maximum ratings Condition D Parameter VDD Pin VDDIO Pin Voltage at any Logic Pin Passive Storage Temp. Range Mechanical Shock Non-Supply Pin -0.3 ≤ 65% rel. H. -50 Duration ≤ 200µs Duration ≤ 1.0ms Free fall onto hard surfaces HBM, at any Pin CDM MM Max -0.3 -0.3 Units V V VDDIO+0.3, <4 +150 10,000 2,000 1.8 V °C g g m D A 3.6 3.
Preliminary Data Sheet BMA400 Page 11 / Confidential 3. Quick Start Guide D A The purpose of this chapter is to help developers who want to start working with the BMA400 by giving you some very basic hands-on application examples to get started. A nd un The communication between application processor AP and BMA400 will happen either over I2C or SPI interface. For more information about the interfaces, read the related chapter 6. Digital Interfaces.
Preliminary Data Sheet BMA400 Page 12 / Confidential de io rN ud ud St ed D C on fid en tia la nd Se e rN io nd la tia en fid A un d ee Se End sleep mode SPI4 No communication: ERROR de St communication: OK C on chipid = 0x90 ? de nd la tia chipid = read_reg(0x00) communication: ERROR End C on fid en Sleep mode SPI4 No Yes communication: OK I2C dummy = read_reg(0x00) A chipid = 0x90 ? Yes SPI un un chipid = read_reg(0x00) I2C power up SPI/I2C D po
Preliminary Data Sheet BMA400 Page 13 / Confidential A –switching from sleep to normal mode, then SPI3 mode, then enable data ready interrupt and map to pin int1 sleep mode SPI4 write_reg(addr=0x19,val=0x02) rN D SPI4 de Switch from sleep mode to normal mode: ACC_CONFIG0 un wait(1500us) ud A A D de rN ud St C on fid en tia la nd Se e ed en fid C on D un la Map data ready interrupt to INT1 pin: INT_CONFIG1 tia Normal mode data conv enabled data ready int to int1 Enable data
Preliminary Data Sheet BMA400 Page 14 / Confidential A -checking communication via chipid, check power mode, read acceleration data if not in sleep mode rN D unknown mode NO End un low power mode A D un ed C on fid en tia la nd Se e C de St tia en fid ud la 6 byte Burst read X,Y,Z data registers in normal or low power mode, calculate X data X = acc_data(0) + 256*acc_data(1) if ( X>2047 ) X=X-4096 on io Se acc_data = read_reg_burst(0x08,6) nd NO rN d un YES ee normal
Preliminary Data Sheet BMA400 Page 15 / Confidential D A 1. Example 3: Testing interrupt engine of BMA400 (example: inactivity interrupt) a.
Preliminary Data Sheet BMA400 Page 16 / Confidential A D rN de ud D un de St d C on fid en tia la nd ee Se rN io nd la tia en fid C on A un d ee Se C on fid en St tia ud la io nd un de rN D A Further steps: The BMA400 has many more capabilities that are described in this document and include FIFO, power saving modes, synchronization capabilities with host processor, data synchronization, many interrupts generation and more features like step counter, etc.
Preliminary Data Sheet BMA400 Page 17 / Confidential 4. Functional Description rN D A Block Diagram io ud rN FIFO ENGINE A ud St un d C on fid en tia la nd ee Se D io nd la tia en fid rN d ee Se INT1, INT2 un de St Interrupt engine C on SPI / I2C D nd acc_filt2 la tia en fid C on DIGITAL INTERFACE DIGITAL SIGNAL FILTERING de C2V, ADC MEMS SENSOR DATA AND SENSORTIME REGISTER acc_filt1 A un de acc_odr BST-BMA400-DS000-00 | Version 0.
Preliminary Data Sheet BMA400 Page 18 / Confidential 4.1. Supply Voltage and Power Management A BMA400 has two distinct power supply pins: rN D VDD is the main power supply. VDDIO is a separate power supply pin used for supplying power for the digital communication interface.
Preliminary Data Sheet BMA400 Page 19 / Confidential 4.2. Power Modes – performance modes D A The power mode and all major settings affecting performance, current consumption, noise and output data rate are controlled in registers ACC_CONFIG0, ACC_CONFIG1 and ACC_CONFIG2. A D rN de ud D un de St d nd ee Se rN io nd la tia en fid on A un d ee Se C on fid en St tia ud la io nd un de rN The BMA400 knows 3 power modes: sleep mode, low-power mode and normal mode.
Preliminary Data Sheet BMA400 Page 20 / Confidential Description b00 b11 Sleep mode (default state after power-up and after reset) I(VDD)< 300nA typ No sensortime, no FIFO read, no data conversions. Register and FIFO content retained, registers readable and writeable b01 Low-power mode I(VDD)< 1.1uA typ Data conversion at 25Hz fixed, noise performance and current consumption tunable by ACC_CONFIG0.
Preliminary Data Sheet BMA400 Page 21 / Confidential Current consumption (uA) in normal mode and low-power mode D A ACC_CONFIG1.osr or ACC_CONFIG0.osr_lp 01 00 14 8 5 3 1.2 1.1 1 0.9 rN 10 D rN ud la io nd A un de Normal mode ACC_CONFIG0. power_mode<1:0> = b10 Low-power mode ACC_CONFIG0. power_mode<1:0> = b01 11 de 6.23 8.81 12.48 6.23 8.81 4.41 6.23 3.12 4.41 3.12 1.56 2.21 2.21 3.12 0.78 1.09 d 1.56 12.5 0.55 0.78 1.09 un 6.23 8.81 1.56 12.
Preliminary Data Sheet BMA400 Page 22 / Confidential Wake-up Interrupt / Auto wake-up rN D A The auto-wakeup function is part of the power management concept of the BMA400. If the wakeup function (only available in low-power mode) changes the power mode to “normal”, the host processor can be notified by an interrupt. This is called “wakeup interrupt”, thus, the two topics “auto wakeup” and “wakeup interrupt” are handled together in this chapter.
Preliminary Data Sheet BMA400 Page 23 / A D rN de un A D rN de un d tia la nd ee Se C on fid en St tia ud la io nd ee Se fid Wake-up interrupt on activity If in low-power mode, BMA400 will wake up when the conditions as defined by the configuration registers are fulfilled.
Preliminary Data Sheet BMA400 Confidential Reference update mode (configured by setting WKUP_INT_CONFIG0.wkup_refu) description of auto-wake references update mode b00 manual update The references (int_wkup_refX/Y/Z) are not updated automatically, they shall be set manually by user b01 one time The references is updated every time at entering low power mode. The first measured acceleration in Low-power mode is used as reference.
Preliminary Data Sheet BMA400 Page 25 / Confidential A D rN de D io nd A un d ee Se rN de un d C on fid en tia la nd ee Se on fid en St tia ud la Wake-up interrupts can be used latched and non-latched (see chapter TBD). Latched and non-latched behavior is shown below. C C on fid en St tia ud la io nd un de rN D A The wake-up on activty is illustrated in the following picture BST-BMA400-DS000-00 | Version 0.
Preliminary Data Sheet BMA400 Page 26 / A nd Auto low-power mode un de rN D A Confidential rN io ud la de St tia ud D un de St d C on fid en tia la nd ee Se rN io nd la tia en fid C on A un d ee Se fid en The following timed and non-timed triggers are supported for automatic switching from Normal mode to Low-power mode: • First data ready: (AUTOLOWPOW_1.auto_lp_timeout =b00) If AUTOLOWPOW_1.
Preliminary Data Sheet BMA400 Page 27 / Confidential The timed timeout trigger can be configured by setting AUTOLOWPOW_1.auto_lp_timeout bits in register according to the table below. D Description timeout disabled, use either AUTOLOWPOW_1.drdy or AUTOLOWPOW_1.gen1_int to switch automatically into lowpower mode de rN b00 A AUTOLOWPOW_1.auto_lp _timeout<1:0> timeout active, BMA400 switching into low-power mode as soon as timeout counter reaches AUTOLOWPOW_1.
Preliminary Data Sheet BMA400 Page 28 / Confidential 4.3. Sensor Data Acceleration Data de rN D A The width of acceleration data is 12 bits given in two´s complement representation in the registers 0x04 to 0x09 (ACC_X_LSB, ACC_X_MSB, ACC_Y_LSB, ACC_Y_MSB, ACC_Z_LSB, ACC_Z_MSB ). The 12 bits for each axis are split into an MSB upper part and an LSB lower part.
Preliminary Data Sheet BMA400 Page 29 / Confidential In low-power mode, only data at 25Hz ODR is available. Depending on the setting of ACC_CONFIG0.osr_lp, noise and current consumption is controllable. D A G-range selection rN The measurement g-range can be selected between 2g and 16g. It can be configured ACC_CONFIG1.acc_range. A D rN ud la io nd un de ACC_CONFIG1.
Preliminary Data Sheet BMA400 Page 30 / Confidential Sensor Time … 0.0031 0.0061 0.012 2.5 de 100 5 4 3 1.250 0.625 0.3125 200 400 800 1600 3200 A d ee fid en [Hz] … 5 6 un Update rate 10 A 81.92 7 D 163.84 327.68 tia [ms] 8 rN … io 21 ud Resolution 22 St 23 sensor_time nd Bit m in la un de rN D A The BMA400 has an integrated sensor timer. The sensor time can be used for synchronization purposes between the external MCU and the sensor.
Preliminary Data Sheet BMA400 Page 31 / Confidential 4.4. FIFO A FIFO description de Stream mode: overwrites oldest data on FIFO full condition FIFO full mode: discards newest data on FIFO full condition D rN io nd The FIFO depth is 1024 byte and supports the following interrupts: FIFO full interrupt FIFO watermark interrupt A un rN D Acceleration data are stored in a 1024Bytes FIFO. The FIFO is written only in normal mode. When FIFO_CONFIG0.
Preliminary Data Sheet BMA400 Page 32 / Confidential FIFO read out un FIFO overflow behavior de rN D A The FIFO can be read out via FIFO_DATA register in a single burst read, this allows a complete reading of the FIFO content within one burst read transaction. FIFO read out is not supported in Sleep mode. FIFO read out is supported in normal and Low-power mode if FIFO_PWR_CONFIG.fifo_read_en = ‘1’. The minimum delay Tfifo_read has to be applied between the write command of FIFO_PWR_CONFIG.
Preliminary Data Sheet BMA400 Page 33 / Confidential Frames rN D A The FIFO captures data in frames, which consist of a header and a payload. Each data frame consists of a one byte header describing properties of the frame, (which data are included in this frame) and the data itself. Beside the data frames, there are control frames, sensortime frames and empty frames.
Preliminary Data Sheet BMA400 Page 34 / Confidential fh_param<2/1/0> indicate whether Z, y or x axis data are stored. rN D A Thus, fh_param<3:0> allows to calculate the amount of data payload following the header. The maximal payload is 6 bytes if all axes are enabled and 12bits are stored. 3bytes payload are needed if all axes are enabled and 8bits are stored. A lesser amount of data is required if one or two axes are disabled.
Preliminary Data Sheet BMA400 Page 35 / Confidential 6 0 5 1 4 3 0 0 sensor_time<7:0> sensor_time<15:8> sensor_time<23:16> D 7 1 rN Bit Header A If fh_param<4:0>= b00000, the header indicates a sensor-time frame to come, its format shown below. un de time 2 0 1 0 0 0 A D rN de io nd fifo_config0_chg A un d ee un de St d ee rN ud la tia - en - 0 0 fifo_config0_chg = b1: The control frame will be inserted when FIFO_CONFIG0.fifo_data_src change becomes active in FIFO.
Preliminary Data Sheet BMA400 Page 36 / Confidential Under-read D A In case the FIFO is under-read (not all frames were taken from the FIFO, but the last frame read was read entirely), the next readout will continue at the frame that was just about to be sent.
Preliminary Data Sheet BMA400 Page 37 / Confidential FIFO flushing A D rN de D A ud rN io nd la FIFO watermark interrupt de un d C on fid en tia la nd ee Se on fid en St tia Watermark interrupt status is asserted when the watermark interrupt condition is satisfied i.e. when the filling level of the FIFO (number of unread bytes in the FIFO) is greater or equal to the watermark level (fifo_bytes_cnt<10:0> ≥ fifo_watermark<10:0>).
Preliminary Data Sheet BMA400 Page 38 / de rN D A Confidential A D rN de D nd A un d ee un de rN io d C on fid en tia la nd ee Se C on fid en St tia ud la Se FIFO watermark interrupt, latched, with reads from FIFO C on fid en St tia ud la io nd un FIFO watermark interrupt, non-latched, with reads from FIFO BST-BMA400-DS000-00 | Version 0.
Preliminary Data Sheet BMA400 Page 39 / Confidential FIFO full interrupt A D rN de D rN de C on fid en tia la nd ee Se C on fid FIFO full interrupt, latched, with reads from FIFO un d en St tia ud la io nd A un d ee Se fid en St tia FIFO full interrupt, non-latched, with reads from FIFO C on ud la io nd un de rN D A Full interrupt status is asserted when the full interrupt condition is satisfied, when the filling level of the FIFO (number of unread bytes in the
Preliminary Data Sheet BMA400 Page 40 / Confidential A 4.5. General Interrupt Pin configuration D Interrupt Pin Mapping de rN The content of the interrupt status registers can be mapped to pins INT1 or INT2, by setting the corresponding bits from the registers INT1_MAP, respectively INT2_MAP or INT12_MAP. To disconnect the features outputs to the external pins, the same corresponding bits must be reset, from the registers, INT1_MAP, respectively INT2_MAP.
Preliminary Data Sheet BMA400 Page 41 / Confidential A D rN de un d en St tia ud la io nd un de rN D A Latched mode In latched mode (INT_CONFIG1.latch_int = 1) an asserted interrupt status in INT_STAT(0/1/2) and the INT pin (the contribution to the ´or´ condition for the INT pin) is cleared by reading the corresponding status register. If the FIFO filling activation condition still holds true then the interrupt status is not cleared.
Preliminary Data Sheet BMA400 Page 42 / Confidential Electrical Interrupt Pin Behavior A Both interrupt pins INT1 and INT2 can be configured to show the desired electrical behavior. D The ‘active’ level of each interrupt pin is determined by the int1_lvl and int2_lvl bits. rN If int1_lvl = 1 / int2_lvl = 1, then pin “INT1” / pin “INT2” are active HIGH. de The characteristic of the output driver of the interrupt pins is configured with bits int1_od and int2_od.
Preliminary Data Sheet BMA400 Page 43 / Confidential 4.6.
Preliminary Data Sheet BMA400 Page 44 / Confidential Generic Interrupt 1 and 2 A The generic interrupts 1 and 2 have the exact same implementation. They are designed to detect activity or inactivity. rN D The generic interrupt monitors acceleration change with respect to a reference, or in other words, the difference between actual acceleration and reference is calculated and compared against a threshold. The comparison is de-noised using a hysteresis.
Preliminary Data Sheet BMA400 Page 45 / Confidential Source for generic interrupt data 0 acc_filt1 A GEN(1/2)INT_CONFIG0.data_src acc_filt2 D 1 de rN The mentioned reference can be static (user defined) or it can be updated dynamically. The reference acceleration registers support reference update modes after comparison evaluation has been done. The mode is set in GEN(1/2)INT_CONFIG0.
Preliminary Data Sheet BMA400 Page 46 / Confidential A hysteresis helps to suppress noise in the decision-making. GEN(1/2)INT_CONFIG0.act_hyst. Following hysteresis configurations for the activity comparison are available: D A GEN(1/2)INT_CONFIG0.
Preliminary Data Sheet BMA400 Page 47 / Confidential Step Detector / Step Counter rN D A The Step Counter algorithm is optimized to high accuracy, while Step Detector is optimized to low latency. Both are running in parallel, once enabled, but the Step Detector interrupt output is mutually exclusive with the Step Counter watermark interrupt. The step counter computation is enabled if INT_CONFIG1.step_int = ‘1’.
Preliminary Data Sheet BMA400 Page 48 / Confidential Activity changed interrupt D A The device provides an “activity changed” interrupt. The activity changed interrupt evaluates acceleration data for a certain activity over a predefined observation period and sets an interrupt after activity change is detected compared to previously evaluated activity. rN The enable signal for this interrupt is INT_CONFIG1.actch_int.
Preliminary Data Sheet BMA400 Page 49 / Confidential Tap Sensing Interrupt D A The tap interrupt is operating on an input data rate of 200Hz. It can detect single and double taps. For configuration, there are the registers TAP_CONFIG and TAP_CONFIG_1. de rN (TAP_CONFIG. tap_sensitivity) allows to modify the threshold for the minimum tap amplitude (TAP_CONFIG_1. quiet) and (TAP_CONFIG_1. quiet_dt) allow to define the duration of quiet times between double taps and between taps.
Preliminary Data Sheet BMA400 Page 50 / Confidential Interrupt engine overrun A D rN de ud D un de St d C on fid en tia la nd ee Se rN io nd la tia en fid C on A un d ee Se C on fid en St tia ud la io nd un de rN D A The interrupt overrun ishall be asserted if filter and interrupt computations cannot be finished in a sample acquisition time. The interrupt status is mapped (mirrored) to all interrupt registers INT_STAT0, INT_STAT1 and INT_STAT2, bit ieng_overrun_stat.
Preliminary Data Sheet BMA400 Page 51 / Confidential Orientation change interrupt D A D ud rN io nd la un d tia la nd ee Se de St tia en fid on Signal flow for orientation change interrupt en C rN de un d ee Se C on fid en St tia ud la io nd A un de rN D A The orientation-change interrupt is enabled by (INT_CONFIG0.orientch_int) = 1. The interrupt is optimized to detect a (screen) orientation change when the product is used in a wearable device or similar application.
Preliminary Data Sheet BMA400 Page 52 / Confidential rN D A The threshold for the orientation change interrupt can be configured in the register ORIENTCH_CONFIG1.orient_thres. The threshold configuration has 8 bits and a resolution of 8mg/LSB. In case the acceleration is above the reference acceleration stored for last position for defined period of time ORIENTCH_CONFIG3.orient_dur; the BMA400 orientation change condition is true.
Preliminary Data Sheet BMA400 Confidential o Last acceleration from acc_filt_lp for stability check Thresholds o Threshold for orientation change: 8 bits, 8 mg/lsb resolution o Stability threshold for stable position: 8bits 8 mg/lsb resolution o Duration for stable orientation: 8bits, 10ms/lsb resolution Reference update mode: o no update, the reference orientation will be not updated automatically, it is set by user o update with acc_filt2 value, the reference orientation is updated with current accelera
Preliminary Data Sheet BMA400 Page 54 / Confidential 4.7. Sensor Self-Test rN D A The BMA400 has a comprehensive self test function for the MEMS element by applying electrostatic forces to the sensor core instead of external accelerations. By actually deflecting the seismic mass, the entire signal path of the sensor can be tested.
Preliminary Data Sheet BMA400 Page 55 / Confidential 4.8. Soft-Reset A D rN de ud D un de St d C on fid en tia la nd ee Se rN io nd la tia en fid C on A un d ee Se C on fid en St tia ud la io nd un de rN D A A softreset can be initiated at any time by writing the command softreset (0xB6) to register CMD. The softreset performs a fundamental reset to the device which is largely equivalent to a power cycle.
Preliminary Data Sheet BMA400 Page 56 / Confidential 5. Register Description 5.1.
Preliminary Data Sheet BMA400 Confidential RegName bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Rst val Access mode 0x21 INT1_MAP drdy_int1 fwm_int1 ffull_int1 gen2_int1 gen1_int1 0x00 RW INT2_MAP drdy_int2 fwm_int2 ffull_int2 gen2_int2 gen1_int2 orientch_int 1 orientch_int 2 wkup_int1 0x22 wkup_int2 0x00 RW 0x23 0x24 0x25 0x26 INT12_MAP INT12_IO_CTRL actch_int2 tap_int2 int2_od ieng_ove rrun_int1 ieng_ove rrun_int2 step_int2 actch_int1 tap_int1 int1_od step_int1 int2_lv
Preliminary Data Sheet BMA400 bit6 bit5 bit4 0x3F act_z_en act_y_en act_x_en data_src 0x57 GEN1INT_CO NFIG0 GEN1INT_CO NFIG1 GEN1INT_CO NFIG2 GEN1INT_CO NFIG3 GEN1INT_CO NFIG3 GEN1INT_CO NFIG4 GEN1INT_CO NFIG5 GEN1INT_CO NFIG6 GEN1INT_CO NFIG7 GEN1INT_CO NFIG8 GEN1INT_CO NFIG9 GEN2INT_CO NFIG0 GEN2INT_CO NFIG1 GEN2INT_CO NFIG2 GEN2INT_CO NFIG3 GEN2INT_CO NFIG3 GEN2INT_CO NFIG4 GEN2INT_CO NFIG5 GEN2INT_CO NFIG6 GEN2INT_CO NFIG7 GEN2INT_CO NFIG8 GEN2INT_CO NFIG9 ACTH_CONFI G0 ACTH_CONFI G1 TAP_CONFI
Register (0x00) CHIPID DESCRIPTION: the register contains the chip identification code read 0x90 to identify product RESET: 0x90 DEFINITION (Go to register map): rN de 5 R 0 4 R 1 1 R 0 0 R 0 ud rN io D A un ud nd la tia en fid D de St d ee Se on C rN io nd la tia en fid A un de St d ee Se C on un nd la tia en fid C on A Register (0x00) CHIPID 7 6 R R 1 0 chipid_7_0 3 2 R R 0 0 chipid_7_0 D Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content
Preliminary Data Sheet BMA400 Page 60 / Confidential Register (0x02) ERR_REG D A DESCRIPTION: reserved RESET: 0x00 DEFINITION (Go to register map): 1 R 0 cmd_err 0 n/a 0 reserved ud rN io 4 n/a 0 A de un nd la 5 n/a 0 D Register (0x02) ERR_REG 7 6 n/a n/a 0 0 reserved 3 2 n/a n/a 0 0 reserved rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content de d ee D rN nd tia la Se 1 R 0 4 R 0 cmd_rdy 0 R 0 int_active de ud St tia en fid 5 n/a 0 io nd la
Preliminary Data Sheet BMA400 Page 61 / Confidential D A cmd_rdy: CMD decoder status.
Preliminary Data Sheet BMA400 Page 62 / Confidential Register (0x05) ACC_X_MSB de Register (0x05) ACC_X_MSB 7 6 n/a n/a 0 0 reserved 3 2 R R 0 0 acc_x_11_8 D 0 R 0 de rN io ud St 1 R 0 4 n/a 0 A 5 n/a 0 un nd la tia Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content rN D A DESCRIPTION: Register for accelerometer data. The ACC_X_LSB-ACC_Z_MSB registers contain the latest data for x, y and z axis of accelerometer.
Preliminary Data Sheet BMA400 Page 63 / Confidential Register (0x07) ACC_Y_MSB de Register (0x07) ACC_Y_MSB 7 6 n/a n/a 0 0 reserved 3 2 R R 0 0 acc_y_11_8 D 0 R 0 de rN io ud St 1 R 0 4 n/a 0 A 5 n/a 0 un nd la tia Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content rN D A DESCRIPTION: Register for accelerometer data. The ACC_X_LSB-ACC_Z_MSB registers contain the latest data for x, y and z axis of accelerometer.
Preliminary Data Sheet BMA400 Page 64 / Confidential Register (0x09) ACC_Z_MSB de Register (0x09) ACC_Z_MSB 7 6 n/a n/a 0 0 reserved 3 2 R R 0 0 acc_z_11_8 D 0 R 0 de rN io ud St 1 R 0 4 n/a 0 A 5 n/a 0 un nd la tia Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content rN D A DESCRIPTION: Register for accelerometer data. The ACC_X_LSB-ACC_Z_MSB registers contain the latest data for x, y and z axis of accelerometer.
Preliminary Data Sheet BMA400 Page 65 / Confidential Register (0x0B) SENSOR_TIME1 D A DESCRIPTION: the register contains the sensor time RESET: 0x00 DEFINITION (Go to register map): 4 R 0 1 R 0 0 R 0 rN io ud la A de un nd 5 R 0 D Register (0x0B) SENSOR_TIME1 7 6 R R 0 0 sensor_time_15_8 3 2 R R 0 0 sensor_time_15_8 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content de D A d 0 R 0 tia la nd ee Se 1 R 0 4 R 0 rN ud St 5 R 0 de io nd la on fi
Preliminary Data Sheet BMA400 Page 66 / Confidential D DESCRIPTION: the register contains event bits.
Preliminary Data Sheet BMA400 Page 67 / Confidential de rN D A ‘0’ = not set; ‘1’ = set ieng_overrun_stat: issued when interrupt calculation could not be finished ffull_int_stat: FIFO full interrupt status: ‘0’ = not set; ‘1’ = set (FIFO full) fwm_int_stat: FIFO watermark interrupt status: ‘0’ = not set; ‘1’ = set drdy_int_stat: data ready interrupt is status: ‘0’ = not set; ‘1’ = set un Register (0x0F) INT_STAT1 A D de C on fid en tia la nd un d ee Se C on fid en step_int_stat: st
Preliminary Data Sheet BMA400 Page 68 / Confidential Register (0x10) INT_STAT2 D A DESCRIPTION: the registers contain the interrupt status bits RESET: 0x00 DEFINITION (Go to register map): 5 n/a 0 Bit Read/Write Reset Value Content 3 n/a 0 reserved 1 R 0 actch_y_int_stat D io ud la rN de un nd 2 R 0 actch_z_int_stat 4 R 0 ieng_overrun_st at 0 R 0 actch_x_int_stat A Register (0x10) INT_STAT2 7 6 n/a n/a 0 0 reserved rN Name Bit Read/Write Reset Value Content de A D rN io nd on Se
Preliminary Data Sheet BMA400 Page 69 / Confidential Register (0x12) FIFO_LENGTH0 D A DESCRIPTION: the register contains the number of bytes stored in FIFO RESET: 0x00 DEFINITION (Go to register map): 4 R 0 1 R 0 0 R 0 rN io ud la A de un nd 5 R 0 D Register (0x12) FIFO_LENGTH0 7 6 R R 0 0 fifo_bytes_cnt_7_0 3 2 R R 0 0 fifo_bytes_cnt_7_0 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content de un d ee A D nd 0 R 0 tia la Se 4 n/a 0 un St tia en fi
Preliminary Data Sheet BMA400 Page 70 / Confidential Register (0x14) FIFO_DATA 1 R 0 0 R 0 rN D A 4 R 0 de St d un Register (0x15) STEP_CNT_0 en 5 R 0 ud la io nd un de Register (0x14) FIFO_DATA 7 6 R R 0 0 fifo_data_field 3 2 R R 0 0 fifo_data_field tia Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content rN D A DESCRIPTION: the register contains the FIFO data. The FIFO data can be read out as burst read.
Preliminary Data Sheet BMA400 Page 71 / Confidential Register (0x16) STEP_CNT_1 D A DESCRIPTION: the register contains the number of steps detected by step counter.
Preliminary Data Sheet BMA400 Page 72 / Confidential Register (0x18) STEP_STAT D A DESCRIPTION: the register filed contains the status STILL(00), WALK(01) or RUN(01) RESET: 0x00 DEFINITION (Go to register map): io 1 R 0 step_stat_field 0 R 0 A 4 n/a 0 D de un nd ud la 5 n/a 0 rN Register (0x18) STEP_STAT 7 6 n/a n/a 0 0 reserved 3 2 n/a n/a 0 0 reserved rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content de rN io ud un d 4 n/a 0 reserved 0 RW 0 nd la 1
Preliminary Data Sheet BMA400 Page 73 / Confidential rN D A filt1_bw: bandwidth selector for filt1 output, valid only for ODRs smaller than 100Hz filt1_bw 0x00 high 0.4x ODR 0x01 low 0.
Preliminary Data Sheet BMA400 Page 74 / Confidential de rN D A settings 0, 1, 2 and 3 allow linearly trading power versus accuracy(noise) acc_range: accelerometer measurement range acc_range 0x00 2g +/-2g measurement range 0x01 4g +/-4g measurement range 0x02 8g +/-8g measurement range 0x03 16g +/-16g measurement range D rN un D rN io un d tia la nd ee C on Se fid en St tia data_src_reg: Select source for data registers data_src_reg 0x00 acc_filt1 variable ODR filter 0x01 acc_filt2
Preliminary Data Sheet BMA400 RW 0 gen2_int_en RW 0 gen1_int_en Confidential RW 0 orientch_int_en n/a 0 reserved A Read/Write Reset Value Content Page 75 / un de rN D orientch_int_en: orientation changed interrupt gen1_int_en: generic interrupt 1 gen2_int_en: generic interrupt 2 ffull_int_en: FIFO full interrupt fwm_int_en: FIFO watermark interrupt drdy_int_en: data ready interrupt A D nd Register (0x20) INT_CONFIG1 D rN ud un St d en tia la nd ee Se fid Register (0x21) INT1_MAP
Preliminary Data Sheet BMA400 Register (0x21) INT1_MAP 7 6 RW RW 0 0 drdy_int1 fwm_int1 Bit Read/Write Reset Value Content 3 RW 0 gen2_int1 rN D A Name Bit Read/Write Reset Value Content Confidential 5 RW 0 ffull_int1 D A D un St 4 RW 0 ieng_overrun_int 2 0 RW 0 wkup_int2 la nd ee 1 RW 0 orientch_int2 tia Se 2 RW 0 gen1_int2 en 3 RW 0 gen2_int2 5 RW 0 ffull_int2 fid Bit Read/Write Reset Value Content d en on fid Register (0x22) INT2_MAP 7 6 RW RW 0 0 drdy_int2 fwm_int2 C Nam
Preliminary Data Sheet BMA400 Page 77 / Confidential A fwm_int2: fifo watermark interrupt is mapped to INT2 drdy_int2: data ready interrupt is mapped to INT2 D Register (0x23) INT12_MAP A D A D un de rN io tia la Se C on fid actch_int1: activity changed interrupt is mapped to INT1 actch_int1 0x00 nomap interrupt not mapped to INT1 0x01 mapped to INT1 interrupt mapped to INT1 nd ee d en St tia tap_int1: tap sensing interrupt is mapped to INT1 tap_int1 0x00 nomap interrupt not mapped
Preliminary Data Sheet BMA400 Page 78 / Confidential rN D A actch_int2 0x00 nomap interrupt not mapped to INT2 0x01 mapped to INT2 interrupt mapped to INT2 Register (0x24) INT12_IO_CTRL A D de un nd la tia en C int2_lvl: INT2 pin output level int2_lvl 0x00 low-act-reset interrupt pin INT2 low-active 0x01 high-act-reset interrupt pin INT2 high-active rN ud St Se ee d en fid A io nd tia la Se int1_od: INT1 pin output driver mode: CMOS or open drain int1_od 0x00 pushpull CMOS push-pull
Preliminary Data Sheet BMA400 Page 79 / Confidential Register (0x26) FIFO_CONFIG0 D A DESCRIPTION: the registers contain the FIFO control and FIFO configuration settings RESET: 0x00 DEFINITION (Go to register map): Register (0x26) FIFO_CONFIG0 7 6 RW RW 0 0 fifo_z_en fifo_y_en 3 2 RW RW 0 0 fifo_data_src fifo_time_en rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 4 RW 0 fifo_8bit_en 0 RW 0 auto_flush rN ud la io nd un de 5 RW 0 fifo_x_en 1 RW 0 fifo_stop_
Preliminary Data Sheet BMA400 Confidential D A fifo_y_en: y-channel data storage control fifo_y_en 0x00 nostore do not store y axis data 0x01 store store y axis data Page 80 / A un de rN fifo_z_en: z-channel data storage control fifo_z_en 0x00 nostore do not store z axis data 0x01 store store z axis data D nd Register (0x27) FIFO_CONFIG1 rN A io de nd un d ee rN 0 RW 0 la on Se fid en fifo_watermark_7_0: lsb of fifo watermark threshold configuration: watermark[byte]= fifo_waterm
Preliminary Data Sheet BMA400 Page 81 / Confidential D A fifo_watermark_10_8: msb of fifo watermark threshold configuration watermark[byte]= fifo_watermark_7_0 + 256*fifo_watermark_10_8 rN Register (0x29) FIFO_PWR_CONFIG A D 0 RW 0 fifo_read_disabl e A ee d un de St 4 n/a 0 rN ud la en fid io nd Register (0x29) FIFO_PWR_CONFIG 7 6 5 n/a n/a n/a 0 0 0 reserved 3 2 1 n/a n/a n/a 0 0 0 reserved tia Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content un de DESC
Preliminary Data Sheet BMA400 Page 82 / Confidential Register (0x2B) AUTOLOWPOW_1 D A DESCRIPTION: the registers contain configurations for auto-low-power condition RESET: 0x00 DEFINITION (Go to register map): io 1 RW 0 gen1_int 0 RW 0 drdy_lowpow_tri g A 4 RW 0 D de un nd ud la 5 RW 0 rN Register (0x2B) AUTOLOWPOW_1 7 6 RW RW 0 0 auto_lp_timeout_thres_3_0 3 2 RW RW 0 0 auto_lp_timeout rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content de ud de St rN io
Preliminary Data Sheet BMA400 Page 83 / Confidential Register (0x2C) AUTOWAKEUP_0 4 RW 0 1 RW 0 0 RW 0 D A 5 RW 0 ud rN io nd un de Register (0x2C) AUTOWAKEUP_0 7 6 RW RW 0 0 wakeup_timeout_thres_11_4 3 2 RW RW 0 0 wakeup_timeout_thres_11_4 la Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content rN D A DESCRIPTION: the register contains configurations for auto-wake-up condition.
Preliminary Data Sheet BMA400 Page 84 / Confidential D A wakeup_timeout_thres_3_0: lsb of wake-up timeout threshold timeout= wakeup_timeout_thres_3_0 + 16*wakeup_timeout_thres_11_4 rN Register (0x2F) WKUP_INT_CONFIG0 A D rN ud 1 RW 0 wkup_refu ud D de St tia rN io nd la Se A un de St d ee en fid 4 RW 0 num_of_sample s 0 RW 0 wkup_refu: wake-up interrupt reference update mode wkup_refu 0x00 manual manual update (reference registers are updated by external MCU) 0x01 onetime one
Preliminary Data Sheet BMA400 Page 85 / Confidential Register (0x30) WKUP_INT_CONFIG1 D A DESCRIPTION: the register contains configurations for wake-up interrupt RESET: 0x00 DEFINITION (Go to register map): Register (0x30) WKUP_INT_CONFIG1 7 6 5 RW RW RW 0 0 0 int_wkup_thres 3 2 1 RW RW RW 0 0 0 int_wkup_thres rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 RW 0 de 4 RW 0 D rN un St nd 0 RW 0 tia la Se ee d en fid
Preliminary Data Sheet BMA400 Page 86 / Confidential Register (0x32) WKUP_INT_CONFIG3 D A DESCRIPTION: the register contains configurations for wake-up interrupt RESET: 0x00 DEFINITION (Go to register map): Register (0x32) WKUP_INT_CONFIG3 7 6 5 RW RW RW 0 0 0 nt_wkup_refy 3 2 1 RW RW RW 0 0 0 nt_wkup_refy rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 RW 0 de A un d ee fid en St tia nt_wkup_refy: reference accelera
Preliminary Data Sheet BMA400 Page 87 / Confidential Register (0x35) ORIENTCH_CONFIG0 D A DESCRIPTION: the registers contain configurations for orientation changed interrupt RESET: 0x00 DEFINITION (Go to register map): Register (0x35) ORIENTCH_CONFIG0 7 6 5 RW RW RW 0 0 0 orient_z_en orient_y_en orient_x_en 3 2 1 RW RW RW 0 0 0 orient_refu stability_mode D A 4 RW 0 orient_data_src 0 RW 0 rN ud la io nd un de rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content de
Preliminary Data Sheet BMA400 Page 88 / Confidential Register (0x36) ORIENTCH_CONFIG1 D A DESCRIPTION: threshold configuration for orientation changed interrupt 8mg/lsb resolution RESET: 0x00 DEFINITION (Go to register map): Register (0x36) ORIENTCH_CONFIG1 7 6 5 RW RW RW 0 0 0 orient_thres 3 2 1 RW RW RW 0 0 0 orient_thres rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 RW 0 de St tia orient_thres: threshold configuration
Preliminary Data Sheet BMA400 Page 89 / Confidential Register (0x38) ORIENTCH_CONFIG3 D A DESCRIPTION: duration for (stable) new orientation before interrupt is triggered RESET: 0x00 DEFINITION (Go to register map): Register (0x38) ORIENTCH_CONFIG3 7 6 5 RW RW RW 0 0 0 orient_dur 3 2 1 RW RW RW 0 0 0 orient_dur rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 RW 0 de D de 4 RW 0 un St nd 0 RW 0 tia la Se ee d en f
Preliminary Data Sheet BMA400 Page 90 / Confidential Register (0x3A) ORIENTCH_CONFIG5 D A DESCRIPTION: the register contains configurations for orientation changed interrupt RESET: 0x00 DEFINITION (Go to register map): Register (0x3A) ORIENTCH_CONFIG5 7 6 5 n/a n/a n/a 0 0 0 reserved 3 2 1 RW RW RW 0 0 0 int_orient_refx_11_8 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 n/a 0 de St tia int_orient_refx_11_8: msb of x-axis
Preliminary Data Sheet BMA400 Page 91 / Confidential Register (0x3C) ORIENTCH_CONFIG7 D A DESCRIPTION: the register contains configurations for orientation changed interrupt RESET: 0x00 DEFINITION (Go to register map): Register (0x3C) ORIENTCH_CONFIG7 7 6 5 n/a n/a n/a 0 0 0 reserved 3 2 1 RW RW RW 0 0 0 int_orient_refy_11_8 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 n/a 0 de St tia int_orient_refy_11_8: msb of y-axis
Preliminary Data Sheet BMA400 Page 92 / Confidential Register (0x3E) ORIENTCH_CONFIG9 D A DESCRIPTION: the registers contain configurations for orientation changed interrupt RESET: 0x00 DEFINITION (Go to register map): Register (0x3E) ORIENTCH_CONFIG9 7 6 5 n/a n/a n/a 0 0 0 reserved 3 2 1 RW RW RW 0 0 0 int_orient_refz_11_8 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 n/a 0 de St tia int_orient_refz_11_8: msb of z-axis
Preliminary Data Sheet BMA400 0x03 Page 93 / Confidential everytime_lp every time automated update by acc_filt_lp rN D A gen1_data_src: data source selection for interrupts evaluation gen1_data_src 0x00 filt1 data source is acc_filt1 0x01 filt2 data source is acc_filt2 A un de gen1_act_x_en: x-axis channel control for interrupt evaluation: ‘0’ - not active; ‘1’ - active gen1_act_y_en: y-axis channel control for interrupt evaluation: ‘0’ - not active; ‘1’ - active gen1_act_z_en: z-axis channel con
Preliminary Data Sheet BMA400 Page 94 / Confidential Register (0x41) GEN1INT_CONFIG2 D A DESCRIPTION: the registers contain configurations for generic interrupt 1 evaluation RESET: 0x00 DEFINITION (Go to register map): Register (0x41) GEN1INT_CONFIG2 7 6 5 RW RW RW 0 0 0 gen1_int_thres 3 2 1 RW RW RW 0 0 0 gen1_int_thres rN A d ee A de nd 0 RW 0 tia la Se 4 RW 0 un St tia en fid ud io nd la Se Register (0x42) GEN1INT_CONFIG3 7 6 5 RW RW RW 0 0 0 gen1_int_dur_15_8 3 2 1 RW RW RW 0
Preliminary Data Sheet BMA400 Page 95 / Confidential Register (0x43) GEN1INT_CONFIG31 D A DESCRIPTION: the registers contain configurations for generic interrupt 1 evaluation RESET: 0x00 DEFINITION (Go to register map): Register (0x43) GEN1INT_CONFIG31 7 6 5 RW RW RW 0 0 0 gen1_int_dur_7_0 3 2 1 RW RW RW 0 0 0 gen1_int_dur_7_0 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 RW 0 de D de 4 RW 0 un St nd 0 RW 0 tia la
Preliminary Data Sheet BMA400 Page 96 / Confidential Register (0x45) GEN1INT_CONFIG5 D A DESCRIPTION: the register contains configurations for generic interrupt 1 evaluation RESET: 0x00 DEFINITION (Go to register map): Register (0x45) GEN1INT_CONFIG5 7 6 5 n/a n/a n/a 0 0 0 reserved 3 2 1 RW RW RW 0 0 0 gen1_int_th_refx_11_8 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 n/a 0 de d ee D de nd 0 RW 0 tia la Se 4 RW
Preliminary Data Sheet BMA400 Page 97 / Confidential Register (0x47) GEN1INT_CONFIG7 D A DESCRIPTION: the registers contain configurations for generic interrupt 1 evaluation RESET: 0x00 DEFINITION (Go to register map): Register (0x47) GEN1INT_CONFIG7 7 6 5 n/a n/a n/a 0 0 0 reserved 3 2 1 RW RW RW 0 0 0 gen1_int_th_refy_11_8 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 n/a 0 de d ee D de nd 0 RW 0 tia la Se 4 RW
Preliminary Data Sheet BMA400 Page 98 / Confidential Register (0x49) GEN1INT_CONFIG9 D A DESCRIPTION: the registers contain configurations for generic interrupt 1 evaluation RESET: 0x00 DEFINITION (Go to register map): Register (0x49) GEN1INT_CONFIG9 7 6 5 n/a n/a n/a 0 0 0 reserved 3 2 1 RW RW RW 0 0 0 gen1_int_th_refz_11_8 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 n/a 0 de d de tia la nd ee Se 4 RW 0 gen2_data
Preliminary Data Sheet BMA400 Page 99 / Confidential rN D A gen2_act_refu: reference update mode for evaluation gen2_act_refu 0x00 manual manual update (reference registers are updated by external MCU) 0x01 onetime one time automated update by the selected data source 0x02 everytime every time automated update by the selected data source 0x03 everytime_lp every time automated update by acc_filt_lp A D nd un de gen2_data_src: data source selection for interrupts evaluation gen2_data_src 0x00 filt1
Preliminary Data Sheet BMA400 Page 100 / Confidential Register (0x4C) GEN2INT_CONFIG2 de Register (0x4C) GEN2INT_CONFIG2 7 6 5 RW RW RW 0 0 0 gen2_int_thres 3 2 1 RW RW RW 0 0 0 gen2_int_thres 4 RW 0 D 0 RW 0 de rN io ud St A un nd la tia Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content rN D A DESCRIPTION: the registers contain configurations for generic interrupt 1 evaluation RESET: 0x00 DEFINITION (Go to register map): D de un d 0 RW 0 en tia la nd
Preliminary Data Sheet BMA400 Page 101 / Confidential Register (0x4E) GEN2INT_CONFIG31 D A DESCRIPTION: the registers contain configurations for generic interrupt 1 evaluation RESET: 0x00 DEFINITION (Go to register map): Register (0x4E) GEN2INT_CONFIG31 7 6 5 RW RW RW 0 0 0 gen2_int_dur_7_0 3 2 1 RW RW RW 0 0 0 gen2_int_dur_7_0 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 RW 0 de D de 4 RW 0 un St nd 0 RW 0 tia la
Preliminary Data Sheet BMA400 Page 102 / Confidential Register (0x50) GEN2INT_CONFIG5 D A DESCRIPTION: the registers contain configurations for generic interrupt 1 evaluation RESET: 0x00 DEFINITION (Go to register map): Register (0x50) GEN2INT_CONFIG5 7 6 5 n/a n/a n/a 0 0 0 reserved 3 2 1 RW RW RW 0 0 0 gen2_int_th_refx_11_8 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 n/a 0 de d ee D de nd 0 RW 0 tia la Se 4 RW
Preliminary Data Sheet BMA400 Page 103 / Confidential Register (0x52) GEN2INT_CONFIG7 D A DESCRIPTION: the registers contain configurations for generic interrupt 1 evaluation RESET: 0x00 DEFINITION (Go to register map): Register (0x52) GEN2INT_CONFIG7 7 6 5 n/a n/a n/a 0 0 0 reserved 3 2 1 RW RW RW 0 0 0 gen2_int_th_refy_11_8 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 n/a 0 de d ee D de nd 0 RW 0 tia la Se 4 RW
Preliminary Data Sheet BMA400 Page 104 / Confidential Register (0x54) GEN2INT_CONFIG9 D A DESCRIPTION: the registers contain configurations for generic interrupt 1 evaluation RESET: 0x00 DEFINITION (Go to register map): Register (0x54) GEN2INT_CONFIG9 7 6 5 n/a n/a n/a 0 0 0 reserved 3 2 1 RW RW RW 0 0 0 gen2_int_th_refz_11_8 rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content D A 0 RW 0 rN ud la io nd un de 4 n/a 0 de d ee D rN de nd 0 RW 0 tia la Se 1
Preliminary Data Sheet BMA400 Page 105 / Confidential Register (0x56) ACTCH_CONFIG1 D A DESCRIPTION: Activity changed interrupt configuration registers RESET: 0x00 DEFINITION (Go to register map): rN io ud la 4 RW 0 actch_data_src 0 RW 0 A de un nd 5 RW 0 actch_x_en 1 RW 0 D Register (0x56) ACTCH_CONFIG1 7 6 RW RW 0 0 actch_z_en actch_y_en 3 2 RW RW 0 0 actch_npts rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content de D rN io ud la d un de St tia en A
Preliminary Data Sheet BMA400 Page 106 / Confidential Register (0x57) TAP_CONFIG D A DESCRIPTION: tap interrupt configuration registers RESET: 0x00 DEFINITION (Go to register map): 1 RW 0 rN io ud la 4 RW 0 sel_axis 0 RW 0 A de un nd 5 n/a 0 D Register (0x57) TAP_CONFIG 7 6 n/a n/a 0 0 reserved 3 2 RW RW 0 0 sel_axis tap_sensitivity rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content de ud fid on D un nd la tia 5 RW 0 quiet_dt 1 RW 1 tics_th en C Regi
Preliminary Data Sheet BMA400 6 data samples for high-low tap signal change time 9 data samples for high-low tap signal change time 12 data samples for high-low tap signal change time 18 daata samples for high-low tap signal change time D A 6 9 12 18 Confidential rN tics_th 0x00 0x01 0x02 0x03 Page 107 / A D rN ud la io nd un de quiet: Minimum quiet time before and after double tap, in data samples This time also defines the longest time interval between two taps so that they are considere
Preliminary Data Sheet BMA400 Page 108 / Confidential Register (0x59) STEP_COUNTER_CONFIG0 D A DESCRIPTION: Reserved RESET: 0x01 DEFINITION (Go to register map): Register (0x59) STEP_COUNTER_CONFIG0 7 6 5 RW RW RW 0 0 0 sccr00 3 2 1 RW RW RW 0 0 0 sccr00 rN de un A A D un St 0 RW 1 C on fid en tia la nd d ee Se 4 RW 0 rN ud io nd la tia en fid on D un de ud St d ee Se Register (0x5A) STEP_COUNTER_CONFIG1 7 6 5 RW RW RW 0 0 1 sccr01 3 2 1 RW RW RW 1 1 0 sccr01 C C
Preliminary Data Sheet BMA400 Page 109 / Confidential Register (0x5B) STEP_COUNTER_CONFIG2 D A DESCRIPTION: Reserved RESET: 0x7B DEFINITION (Go to register map): Register (0x5B) STEP_COUNTER_CONFIG2 7 6 5 RW RW RW 0 1 1 sccr02 3 2 1 RW RW RW 1 0 1 sccr02 rN de un A D A 0 RW 0 un St C on fid en tia la nd d ee Se C 4 RW 1 rN ud io nd la tia en fid D un de ud St d ee Register (0x5C) STEP_COUNTER_CONFIG3 7 6 5 RW RW RW 1 1 0 sccr03 3 2 1 RW RW RW 0 1 0 sccr03 on on C S
Preliminary Data Sheet BMA400 Page 110 / Confidential Register (0x5D) STEP_COUNTER_CONFIG4 D A DESCRIPTION: Reserved RESET: 0x44 DEFINITION (Go to register map): Register (0x5D) STEP_COUNTER_CONFIG4 7 6 5 RW RW RW 0 1 0 sccr04 3 2 1 RW RW RW 0 1 0 sccr04 rN de un A D A 0 RW 1 un St C on fid en tia la nd d ee Se C 4 RW 0 rN ud io nd la tia en fid D un de ud St d ee Register (0x5E) STEP_COUNTER_CONFIG5 7 6 5 RW RW RW 0 0 0 sccr05 3 2 1 RW RW RW 0 0 0 sccr05 on on C S
Preliminary Data Sheet BMA400 Page 111 / Confidential Register (0x5F) STEP_COUNTER_CONFIG6 D A DESCRIPTION: Reserved RESET: 0x3B DEFINITION (Go to register map): Register (0x5F) STEP_COUNTER_CONFIG6 7 6 5 RW RW RW 0 0 1 sccr06 3 2 1 RW RW RW 1 0 1 sccr06 rN de un A D A 0 RW 0 un St C on fid en tia la nd d ee Se C 4 RW 1 rN ud io nd la tia en fid D un de ud St d ee Register (0x60) STEP_COUNTER_CONFIG7 7 6 5 RW RW RW 0 1 1 sccr07 3 2 1 RW RW RW 1 0 1 sccr07 on on C S
Preliminary Data Sheet BMA400 Page 112 / Confidential Register (0x61) STEP_COUNTER_CONFIG8 D A DESCRIPTION: Reserved RESET: 0xDB DEFINITION (Go to register map): Register (0x61) STEP_COUNTER_CONFIG8 7 6 5 RW RW RW 1 1 0 sccr08 3 2 1 RW RW RW 1 0 1 sccr08 rN de un A D A 0 RW 1 un St C on fid en tia la nd d ee Se C 4 RW 1 rN ud io nd la tia en fid D un de ud St d ee Register (0x62) STEP_COUNTER_CONFIG9 7 6 5 RW RW RW 0 1 1 sccr09 3 2 1 RW RW RW 1 0 1 sccr09 on on C S
Preliminary Data Sheet BMA400 Page 113 / Confidential Register (0x63) STEP_COUNTER_CONFIG10 D A DESCRIPTION: Reserved RESET: 0x3F DEFINITION (Go to register map): Register (0x63) STEP_COUNTER_CONFIG10 7 6 5 RW RW RW 0 0 1 sccr10 3 2 1 RW RW RW 1 1 1 sccr10 rN de un A D A 0 RW 0 un St C on fid en tia la nd d ee Se C 4 RW 0 rN ud io nd la tia en fid D un de ud St d ee Register (0x64) STEP_COUNTER_CONFIG11 7 6 5 RW RW RW 0 1 1 sccr11 3 2 1 RW RW RW 1 1 0 sccr11 on on C
Preliminary Data Sheet BMA400 Page 114 / Confidential Register (0x65) STEP_COUNTER_CONFIG12 D A DESCRIPTION: Reserved RESET: 0xCD DEFINITION (Go to register map): Register (0x65) STEP_COUNTER_CONFIG12 7 6 5 RW RW RW 1 1 0 sccr12 3 2 1 RW RW RW 1 1 0 sccr12 rN de un A D A 0 RW 1 un St C on fid en tia la nd d ee Se C 4 RW 0 rN ud io nd la tia en fid D un de ud St d ee Register (0x66) STEP_COUNTER_CONFIG13 7 6 5 RW RW RW 0 0 1 sccr13 3 2 1 RW RW RW 0 1 1 sccr13 on on C
Preliminary Data Sheet BMA400 Page 115 / Confidential Register (0x67) STEP_COUNTER_CONFIG14 D A DESCRIPTION: Reserved RESET: 0x19 DEFINITION (Go to register map): Register (0x67) STEP_COUNTER_CONFIG14 7 6 5 RW RW RW 0 0 0 sccr14 3 2 1 RW RW RW 1 0 0 sccr14 rN de un A D A 0 RW 0 un St C on fid en tia la nd d ee Se C 4 RW 1 rN ud io nd la tia en fid D un de ud St d ee Register (0x68) STEP_COUNTER_CONFIG15 7 6 5 RW RW RW 1 0 0 sccr15 3 2 1 RW RW RW 0 1 1 sccr15 on on C
Preliminary Data Sheet BMA400 Page 116 / Confidential Register (0x69) STEP_COUNTER_CONFIG16 D A DESCRIPTION: Reserved RESET: 0xA0 DEFINITION (Go to register map): Register (0x69) STEP_COUNTER_CONFIG16 7 6 5 RW RW RW 1 0 1 sccr16 3 2 1 RW RW RW 0 0 0 sccr16 rN de un A D A 0 RW 1 un St C on fid en tia la nd d ee Se C 4 RW 0 rN ud io nd la tia en fid D un de ud St d ee Register (0x6A) STEP_COUNTER_CONFIG17 7 6 5 RW RW RW 1 1 0 sccr17 3 2 1 RW RW RW 0 0 1 sccr17 on on C
Preliminary Data Sheet BMA400 Page 117 / Confidential Register (0x6B) STEP_COUNTER_CONFIG18 D A DESCRIPTION: Reserved RESET: 0x0E DEFINITION (Go to register map): Register (0x6B) STEP_COUNTER_CONFIG18 7 6 5 RW RW RW 0 0 0 sccr18 3 2 1 RW RW RW 1 1 1 sccr18 rN de un A D A 0 RW 0 un St C on fid en tia la nd d ee Se C 4 RW 0 rN ud io nd la tia en fid D un de ud St d ee Register (0x6C) STEP_COUNTER_CONFIG19 7 6 5 RW RW RW 0 0 0 sccr19 3 2 1 RW RW RW 1 1 0 sccr19 on on C
Preliminary Data Sheet BMA400 Page 118 / Confidential Register (0x6D) STEP_COUNTER_CONFIG20 D A DESCRIPTION: Reserved RESET: 0x3C DEFINITION (Go to register map): Register (0x6D) STEP_COUNTER_CONFIG20 7 6 5 RW RW RW 0 0 1 sccr20 3 2 1 RW RW RW 1 1 0 sccr20 rN de un A D A 0 RW 0 un St C on fid en tia la nd d ee Se C 4 RW 1 rN ud io nd la tia en fid D un de ud St d ee Register (0x6E) STEP_COUNTER_CONFIG21 7 6 5 RW RW RW 1 1 1 sccr21 3 2 1 RW RW RW 0 0 0 sccr21 on on C
Preliminary Data Sheet BMA400 Page 119 / Confidential Register (0x6F) STEP_COUNTER_CONFIG22 D A DESCRIPTION: Reserved RESET: 0x00 DEFINITION (Go to register map): Register (0x6F) STEP_COUNTER_CONFIG22 7 6 5 RW RW RW 0 0 0 sccr22 3 2 1 RW RW RW 0 0 0 sccr22 rN de un A D A 0 RW 1 un St C on fid en tia la nd d ee Se C 4 RW 1 rN ud io nd la tia en fid D un de ud St d ee Register (0x70) STEP_COUNTER_CONFIG23 7 6 5 RW RW RW 1 1 1 sccr23 3 2 1 RW RW RW 0 1 1 sccr23 on on C
Preliminary Data Sheet BMA400 Page 120 / Confidential Register (0x71) STEP_COUNTER_CONFIG24 D A DESCRIPTION: Reserved RESET: 0x00 DEFINITION (Go to register map): Register (0x71) STEP_COUNTER_CONFIG24 7 6 5 RW RW RW 0 0 0 sccr24 3 2 1 RW RW RW 0 0 0 sccr24 rN de un ud A d D C on fid en tia la nd ee Se C spi3: Configure SPI Interface Mode for primary interface spi3 0x00 spi4 SPI 4-wire mode 0x01 spi3 SPI 3-wire mode 0 RW 0 spi3 un 1 n/a 0 4 n/a 0 rN io ud St 5 n/a 0 A un nd
Preliminary Data Sheet BMA400 Page 121 / Confidential Register (0x7D) SELF_TEST D A DESCRIPTION: Settings for the sensor self-test configuration and trigger RESET: 0x00 DEFINITION (Go to register map): io ud A 0 RW 0 acc_self_test_en _x ud D un d C on fid en tia la nd ee Se de St tia en fid C acc_self_test_sign: select sign of self-test excitation acc_self_test_sign 0x00 negative negative 0x01 positive positive rN io nd la Se acc_self_test_en_z: trigger self test for Z axi
Preliminary Data Sheet BMA400 Page 122 / Confidential Register (0x7E) CMD D 1 RW 0 0 RW 0 A 4 RW 0 io D de un nd ud la 5 RW 0 rN Register (0x7E) CMD 7 6 RW RW 0 0 cmd 3 2 RW RW 0 0 cmd rN Name Bit Read/Write Reset Value Content Bit Read/Write Reset Value Content A DESCRIPTION: Command Register RESET: 0x00 DEFINITION (Go to register map): de D rN ud la io nd A un d ee Se de un en St tia The device supports a command set to trigger certain activities and state transitions
Preliminary Data Sheet BMA400 Page 123 / Confidential 6. Digital Interfaces 6.1. Interface Name I/O Type 1 SDO Digital I/O 2 SDX Digital I/O 5 INT1 Digital I/O INT2 Digital I/O 10 CSB Digital in Serial data output in SPI Address select in I²C mode see chapter 7.
Preliminary Data Sheet BMA400 Page 124 / Confidential 6.2. Interface I2C/SPI Protocol Selection A The protocol is automatically selected based on the chip select CSB pin behavior after power-up. de rN D At reset / power-up, BMA400 is in I2C mode. If CSB is connected to VDDIO during power-up and not changed the sensor interface works in I2C mode. For using I2C, it is recommended to hard-wire the CSB line to VDDIO.
Preliminary Data Sheet BMA400 Page 125 / Confidential The following figure shows the definition of the SPI timings: D rN CSB de tSCKL tSCKH io ud la D tSDI_hold tSDI_setup tSDO_OD de St tia A un nd SDI rN SCK ee d en SPI timing diagram un SDO tCSB_hold A tCSB_setup D A ud rN io nd la Se de un d nd ee Se on fid en St tia Two configurations of the SPI interface are supported by the BMA400: 4-wire and 3-wire. The same protocol is used by both configurations.
Preliminary Data Sheet BMA400 Page 126 / Confidential A CSB A D6 A D5 A D4 A D3 A D2 A D1 A D0 DI6 DI5 DI4 DI1 DI0 X io D A Data 4-wire basic SPI write sequence (mode ´00´) ud la DI2 X R/W + register address nd logical DI3 Z un X DI7 rN SDO R/W de X SDX rN D SCX de DI4 DI3 DI2 DI1 DI0 R/W A D ud St DI5 rN io nd la DI6 A D6 A D5 A D4 A D3 A D2 A D1 A D0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 de X DI7 X DI0 Data (address l) address data nd on R/W + re
Preliminary Data Sheet BMA400 Page 127 / Confidential CSB 7 SDO A D6 A D5 A D4 A D3 A D2 A D1 A D0 X 3 2 1 0 D R/W 5 rN X SDX 6 A SCX X DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 de Z R/W + register address Dummy Dummy Read Data un logical X 4-wire basic SPI read sequence (mode ´00´) A D rN ud la io nd The data bits are used as follows: R/W: Read/Write bit. When 0, the data SDI is written into the chip. When 1, the data SDO from the chip is read.
Preliminary Data Sheet BMA400 Confidential D A CSB Page 128 / AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 D A DI0 rN de A io nd ud la St tia un nd C on fid en tia la Se ee d en fid C on DI1 un d ee Se C on fid en St tia ud la io nd 3-wire basic SPI read or write sequence (mode ´11´) DI2 D AD5 rN AD6 un RW de SDI de rN SCK BST-BMA400-DS000-00 | Version 0.
Preliminary Data Sheet BMA400 Page 129 / Confidential 6.4. Primary I2C Interface D rN ud la io nd A un de rN D A The I²C bus uses SCL (= SCx pin, serial clock) and SDA (= SDx pin, serial data input and output) signal lines. Both lines are connected to VDDIO externally via pull-up resistors so that they are pulled high when the bus is free. The default I²C address of the device is b001010X .
Preliminary Data Sheet BMA400 Page 130 / Confidential A The figure below shows the definition of the I²C timings A D rN io de I²C timing diagram A io nd Se tSUSTO un d ee fid en St tia tSUSTA The I²C protocol works as follows: on tSUDAT ud la SDA tHIGH tHDDAT tr nd tHDSTA un SCL rN de St tia ud la START: Data transmission on the bus begins with a high to low transition on the SDA line while SCL is held high (start condition (S) indicated by I²C bus master).
Preliminary Data Sheet BMA400 Page 131 / Confidential I²C write access: I²C write access can be used to write a data byte in one sequence.
Preliminary Data Sheet BMA400 0 1 0 0 S Slave Adress 0 0 1 0 0 L 0 0 S 1 0 0 1 0 ACK 1 Register data - address 0x05 R/W ACK 1 0 d7 d6 d5 d4 d3 d2 Confidential d1 Register data - address 0x06 ACK d0 d7 d6 d5 d4 d3 d2 d1 NACK Stop d0 rN Start Register address (0x05) R/W ACK 1 A 0 D Slave Adress Start Page 132 / A D rN de ud D un de St d C on fid en tia la nd ee Se rN io nd la tia en fid C on A un d ee Se C on fid en St tia ud la
Preliminary Data Sheet BMA400 Page 133 / Confidential 7. Pin-out and Connection Diagrams rN D A 7.1. Pin-out Pads visible! 12 SCX A D de la tia en VDD VDD VDD GND GND CSB GND GND DNC (float) SCK SCL fid Power supply for analog & digital domain (1.62V … 3.
Preliminary Data Sheet BMA400 Page 134 / Confidential 7.2.
Preliminary Data Sheet BMA400 Page 135 / Confidential I2C 2 VDDIO 3 11 10 CSB BMA400 9 GND Top View 8 (Pads not visible!) 4 6 7 VDD VDD rN GND ud la io 100nF 5 100nF GNDIO A nd 12 D SDX un VDDIO 1 INT2 SDA SDO INT1 =1 =0 de I2C_ID.
Preliminary Data Sheet BMA400 Page 136 / Confidential 8. Package A D rN de ud D un de St d C on fid en tia la nd ee Se rN io nd la tia en fid C on A un d ee Se C on fid en St tia ud la io nd un de rN D A 8.1. Package outline dimensions BST-BMA400-DS000-00 | Version 0.1 | November 2017 Bosch Sensortec © Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights.
Preliminary Data Sheet BMA400 Page 137 / Confidential 8.2. Sensing axis orientation rN D A If the sensor is accelerated in the indicated directions, the corresponding channel will deliver a positive acceleration signal (dynamic acceleration). If the sensor is at rest and the force of gravity is acting along the indicated directions, the output of the corresponding channel will be negative (static acceleration).
Preliminary Data Sheet BMA400 Page 138 / Confidential BMA400 A D rN de ud D un de St d C on fid en tia la nd ee Se rN io nd la tia en fid C on A un d ee Se C on fid en St tia ud la io nd un de rN D A For reference the figure below shows the device orientation with an integrated BMA400. BST-BMA400-DS000-00 | Version 0.1 | November 2017 Bosch Sensortec © Bosch Sensortec GmbH reserves all rights even in the event of industrial property rights.
Preliminary Data Sheet BMA400 Page 139 / Confidential 8.3. Landing pattern recommendation A D rN de ud D un de St d C on fid en tia la nd ee Se rN io nd la tia en fid C on A un d ee Se C on fid en St tia ud la io nd un de rN D A The recommended landing pattern for the BMA400 on customer’s PCB is given in the following figure. It is recommended to avoid any wiring underneath the BMA400 (shaded area). BST-BMA400-DS000-00 | Version 0.
Preliminary Data Sheet BMA400 Page 140 / Confidential Marking of Engineering Samples(A,C) BMA400 internal use only E Identifies Engineering Samples Sample ID NCC ‘N’ to be replaced by ‘A’,’C’, sample status ‘CC’ defines lot number Pin 1 identifier top side • ◤ Pin 1 identifier bottom side D de un la Triangle points in the direction of pin 1 C on fid en tia C Se ◤ -- nd ee d en • rN 3 alphanumeric digits, variable to generate trace-code.
Preliminary Data Sheet BMA400 Page 141 / Confidential 8.5.
Preliminary Data Sheet BMA400 Page 142 / Confidential 8.6. Handling instructions rN D A Micromechanical sensors are designed to sense acceleration with high accuracy even at low amplitudes and contain highly sensitive structures inside the sensor element. The MEMS sensor can tolerate mechanical shocks up to several thousand g's. However, these limits might be exceeded in conditions with extreme shock loads such as e.g.
Preliminary Data Sheet BMA400 Page 143 / Confidential 8.7. Environmental safety D A The BMA400 sensor meets the requirements of the EC restriction of hazardous substances (RoHS) directive, see also: de rN Directive 2011/65/EU of the European Parliament and of the Council of 8 September 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment. un Halogen content A rN io Internal package structure D nd The BMA400 is halogen-free.
Preliminary Data Sheet BMA400 Page 144 / Confidential 9. Legal disclaimer 9.1. Engineering samples 9.2. Product use A un de rN D A Engineering Samples are marked with an asterisk (*) or (e). Samples may vary from the valid technical specifications of the product series contained in this data sheet. They are therefore not intended or fit for resale to third parties or for use in end products. Their sole purpose is internal client testing.
Preliminary Data Sheet BMA400 Page 145 / Confidential 10.Document history and modification Chapter Description of modification/changes Date Document creation 03 Nov 2017 A Rev. No A D rN de D ud rN io nd la un d C on fid en tia la nd ee Se de St tia en fid C on A un d ee Se C on fid en St tia ud la io nd un de rN D 0.1 Bosch Sensortec GmbH Gerhard-Kindler-Strasse 9 72770 Reutlingen / Germany contact@bosch-sensortec.com www.bosch-sensortec.
