Datasheet

Document Number: 001-89638 Rev. *G Page 7 of 34
PSoC
®
4: PSoC 4000 Family
Datasheet
Pinouts
All port pins support GPIO. Ports 0, 1, and 2 support CSD CapSense and analog multiplexed bus connections. TCPWM functions and Alternate Functions are multiplexed
with port pins as follows for the five PSoC 4000 packages.
Table 1. Pin Descriptions
28-Pin SSOP 24-Pin QFN 16-Pin QFN 16-Pin SOIC 8-Pin SOIC
Pin Name Pin Name Pin Name Pin Name Pin Name TCPWM Signals Alternate Functions
20 VSS
21 P0.0/TRIN0 1 P0.0/TRIN0 TRIN0: Trigger Input
0
22 P0.1/TRIN1/CMPO
_0
2 P0.1/TRIN1/CMPO
_0
1 P0.1/TRIN1/CMPO
_0
3 P0.1/TRIN1/CMPO
_0
TRIN1: Trigger Input
1
CMPO_0: Sense
Comp Out
23 P0.2/TRIN2 3 P0.2/TRIN2 2 P0.2/TRIN2 4 P0.2/TRIN2 TRIN2: Trigger Input
2
24 P0.3/TRIN3 4 P0.3/TRIN3 TRIN3: Trigger Input
3
25 P0.4/TRIN4/CMPO
_0/EXT_CLK
5 P0.4/TRIN4/CMPO
_0/EXT_CLK
3 P0.4/TRIN4/CMPO
_0/EXT_CLK
5 P0.4/TRIN4/CMPO
_0/EXT_CLK
2 P0.4/TRIN4/CMPO
_0/EXT_CLK
TRIN4: Trigger Input
4
CMPO_0: Sense
Comp Out, External
Clock, CMOD Cap
26 VCC 6 VCC 4 VCC 6 VCC 3 VCC
27 VDD 7 VDD 6 VDD 7 VDD 4 VDD
28 VSS 8 VSS 7 VSS 8 VSS 5 VSS
1 P0.5 9 P0.5 5 VDDIO 9 P0.5
2 P0.6 10 P0.6 8 P0.6 10 P0.6
3P0.711P0.7
4P1.012P1.0
5 P1.1/OUT0 13 P1.1/OUT0 9 P1.1/OUT0 11 P1.1/OUT0 6 P1.1/OUT0 OUT0: PWM OUT 0
6 P1.2/SCL 14 P1.2/SCL 10 P1.2/SCL 12 P1.2/SCL I2C Clock
7 P1.3/SDA 15 P1.3/SDA 11 P1.3/SDA 13 P1.3/SDA I2C Data
8 P1.4/UND0 16 P1.4/UND0 UND0: Underflow
Out
9 P1.5/OVF0 17 P1.5/OVF0 OVF0: Overflow Out
10 P1.6/OVF0/UND0/n
OUT0
/CMPO_0
18 P1.6/OVF0/UND0/n
OUT0
/CMPO_0
12 P1.6/OVF0/UND0/n
OUT0/CMPO_0
14 P1.6/OVF0/UND0/n
OUT0/CMPO_0
7 P1.6/OVF0/UND0/n
OUT0/CMPO_0
nOUT0:
Complement of
OUT0, UND0,
OVF0 as above
CMPO_0: Sense
Comp Out, Internal
Reset function
[1]
Note
1. Must not have load to ground during POR (should be an output).