Datasheet

PSoC
®
4: PSoC 4000 Family
Datasheet
Document Number: 001-89638 Rev. *G Page 4 of 34
Figure 2. Block Diagram
PSoC 4000 devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4000 devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4000 family provides a level of security not
possible with multi-chip application solutions or with microcon-
trollers. It has the following advantages:
■ Allows disabling of debug features
■ Robust flash protection
■ Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
The debug circuits are enabled by default and can only be
disabled in firmware. If they are not enabled, the only way to
re-enable them is to erase the entire device, clear flash
protection, and reprogram the device with new firmware that
enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4000, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4000 allows the
customer to make.
Deep Sleep
Active/ Sleep
CPU Subsystem
SRAM
2 KB
SRAM Controller
ROM
4 KB
ROM Controller
Flash
16 KB
Read Accelerator
SPCIFSWD/TC
NVIC, IRQMX
Cortex
M0
16 MHz
MUL
System Interconnect (
Single/Multi Layer AHB
)
I/O Subsystem
20 x GPIOs
IOSS GPIO (4x ports)
Peripherals
Peripheral Interconnect (MMIO)
PCLK
PSoC 4000
32-bit
AHB- Lite
DFT Logic
Test
DFT Analog
System Resources
Lite
Power
Clock
WDT
ILO
Reset
Clock Control
IMO
Sleep Control
PWRSYS
REFPOR
WIC
Reset Control
XRES
1x SCB-I2C
CapSense
High Speed I/O Matrix
Power Modes
1x TCPWM