Technical information

The two PA-8500 processors on either side communicate with each other and the Mustang ASIC
(interfaces the processors with I/O and memory) over a 120-Mhz bus (Runway bus). There are two
Runway busses (C-side and D-side). Because of timing and pin constraints these busses are not
crosschecked, but any subsequent transactions to the memory, I/O, or Console Controller are checked.
The Runway bus is a 64-bit wide bi-directional multiplexed address/data bus supporting split response
transactions and out-of-order transaction completion, thus optimizing system performance and enhancing
processing of multiple operations simultaneously. All cache coherency operations are performed on the
bus and made visible to all entities on the bus, thus external snoop tags are not required.
The two Mustang ASICs (C and D) transfer memory requests to the 60-MHz H-Bus running between the
Mustang ASICs and the memory modules. The H-Bus has a 128-bit + parity wide data bus that is shared
between the C and D sides. There are separate C and D side address/control lines. For data operations,
the C-side device drives 64 bits of data and the D-side device drives the other 64 bits. Each Mustang
ASIC receives the full 128-bit data and can thus check the data driven on writes. On reads, the data is
cross checked by custom ASICs on the memory cards. It is also parity protected.
During system boot up time, the CPUs fetch their instructions for initialization from a boot prom prior to
execution from main memory. This boot prom is a single AMD 29F040 (512Kx8bit) flash PROM. This
PROM is duplicated from C to D side and is accessed over the dedicated F-Bus (the flash bus between
the Mustang ASICs and the CPU's flash PROM). The main bus is 16 bits wide for addressing the PROM
Theory of Operation
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