Specifications

Key to multiword DMA timing data (all times in nsec)
Mode 0
Label Parameter Min. Max.
T0 Cycle time 480 —
TC DMACK to DMREQ delay — —
TD DIOR–/DIOW– 16-bit pulse width 215 —
TE DIOR– data access — 150
TF DIOR– data hold 5 20
TG DIOW– data setup 100 —
TH DIOR– data hold 20 —
TI DMACK to DIOR–/DIOW– setup 0 —
TJ DIOR–/DIOW– to DMACK hold 20 —
TKr DIOR– negated pulse width 50 —
TKw DIOW– negated pulse width 215 —
TLr DIOR– to DMREQ delay — 120
TLw DIOW– to DMREQ delay — 40
DMARQ
DMACK–
Read
DD0–DD15
Write
DD0–DD15
TO
TI
TL
TD TK
TJ
TE
TF
TG
TH
DIOR–
DIOW–
Figure 15. Multiword DMA transfer timing
ATA Interface Reference Manual, Rev. C 69