Specifications

Key to single-word DMA timing data (all times in nsec)
Label Parameter Mode 0 Mode 1 Mode 2
T0 Cycle Time 960 480 240
TC DMACK to DMREQ delay 200* 100* 80*
TD DIOR–/DIOW– 16-bit pulse 480 240 120
TE DIOR– data access 250* 150* 60*
TF DIOR– data hold 5 5 5
TG DIOW– data setup 250 100 35
TH DIOW– data hold 50 30 20
TI DMACK to DIOR–/DIOW– setup 0 0 0
TJ DIOR–/DIOW– to DMACK hold 0 0 0
TS DIOR– setup TD-TE TD-TE TD-TE
Note. All timings indicate minimum times except for those marked with
an asterisk (*), which show
maximum allowable times.
DMARQ
DMACK–
DIOR – /DIOW –
Read
DD0–DD15
Write
DD0–DD15
TO
TD
TG
TE TF
TH
TJTI
TC
Figure 14. Single-word DMA transfer timing
68 ATA Interface Reference Manual, Rev. C