Specifications

Key to PIO timing data (all times in nsec)
Label Parameter Mode 0 Mode 1 Mode 2
T0 Cycle Time 600 383 240
T1 DIOR–/DIOW– setup address valid 70 50 30
T2 DIOR–/DIOW– pulse width: 16-bit
8-bit
165
290
125
290
100
290
T3 DIOW– data setup 60 45 30
T4 DIOW– data hold 30 20 15
T5 DIOR– data setup 50 35 20
T6 DIOR– data hold 5 5 5
T7 Addr. valid to IOCS16– assertion 90* 50* 40*
T8 Addr. valid to IOCS16– negation 60* 45* 30*
T9 DOIR–/DIOW– address valid hold 20 15 10
Note. All timings indicate minimum times except for those marked with
an asterisk (*), which show
maximum allowable times.
Address
Valid *1
DIOR–/DIOW–
Write Data
Valid *2
Read Data
Valid *2
IOCS16–
*1 Drive Address consists of signals CS1FX–, CS3FX–, and DA2–DA0
*2 Data consists of DD0–DD15 (16-bit) or DD0–DD7 (8-bit)
T0
T9
T4T3
T5 T6
T2T1
T7
T8
Figure 12. PIO data transfer timing (to and from drive)
66 ATA Interface Reference Manual, Rev. C