Specifications

6.0 ATA Interface timing diagrams

The following symbols are used in the timing specifications for the ATA

interface. The host is responsible for providing cable deskewing for all

signals originating from the controller. The drive provides cable deskewing

for all signals originating from the host.

Within these diagrams, all timing specifications are in nanoseconds

(nsec), unless otherwise specified. Timing parameters designated with

an asterisk (*) represent

maximum

allowable times. All other parameters

represent

minimum

times.

signal transition (asserted or negated) *

data transition (asserted or negated)

the alternate condition if a signal is shown with no change

a degree of uncertainty as to when a signal is asserted

a degree of uncertainty as to when a signal is negated

Nominal clock period

Bit setting = 1- - - -

Bit setting = 0- - - -

Bit setting = 1- - - -

—

*Both active high and active low signals are shown with the asserted

condition toward the top of the page and the negated condition toward

the bottom of the page (see diagrams below):

Assert

Negate

Assert Negate

TEST

(Active High)

TEST–

(Active Low)

Figure 11. Timing diagram signal conventions

ATA Interface Reference Manual, Rev. C 65