Specifications

4.13 Status register
CS1FX– = 1 DA2 = 1
CS3FX– = 0 DA1 = 1
Mode = Read Only DA0 = 1
PC-AT I/O port address: 1F7
H
This register contains either the drive status or the controller status. It is
updated at the completion of each command. If the host reads this
register while an interrupt is pending, it clears the interrupt.
The bits in the Status register are defined below:
Bit 7 6 5 4 3 2 1 0
Name BSY DRDY DWF DSC DRQ CORR IDX ERR
BSY is the busy bit. It is set to 1 whenever the drive has access to the
command block. When it is set to 1:
No other bits are valid.
The host is locked out of reading shared registers; the Status
register is read instead.
The BSY bit is set to 1 under the following circumstances:
At the assertion of the RESET– signal on the interface
At the assertion of the SRST bit in the Device Control register
Immediately upon host write to the Command register
DRDY is the drive ready indicator bit. This bit is set to 0 at power up and
remains set at 0 until the drive is ready to accept a command.
DWF is the drive write fault bit. When there is a write fault error, this
bit is set to 1 and is not changed until the Status register is read
by the host, at which time the bit again indicates the current write
fault status.
DSC is the drive seek complete bit. It is set to 1 when the disc drive
is not seeking.
ATA Interface Reference Manual, Rev. C 21