Specifications

The Device Control register contains the two control bits shown below
(X indicates bits that are not used):
Bit 7 6 5 4 3 2 1 0
Name X X X X 1 SRST nIEN 0
nIEN is the enable bit for the drive interrupt to the host.
When this bit is set to 0 and the drive is selected, the host
interrupt, INTRQ, is enabled, through a tristate buffer, to the host.
When nIEN is set to 1, or the drive is not selected, the INTRQ
pin is in a high-impedance state, regardless of the presence or
absence of a pending interrupt.
SRST is the host software reset bit. When it is set to 1, the drive is reset.
When it is set to 0, the drive is enabled. If two drives are
daisy-chained on the interface, this bit resets and enables both
drives simultaneously.
4.7 Drive Address register
CS1FX– = 0 DA2 = 1
CS3FX– = 1 DA1 = 1
DA0 = 1 Mode = Read Only
PC-AT I/O port address: 3F7
H
This register contains the drive select and head select signals of the
currently selected drive. The bits in this register are as follows:
Bit 7 6 5 4 3 2 1 0
Name HiZ nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0
HiZ is reserved and is not driven by the drive. When the host reads
the Drive Address register, the HiZ bit must be in a high-imped-
ance state.
nWTG is the write gate bit, which is set to 1 during a Write command.
nHS3 through nHS0
are the one’s complement of the binary-coded address of the
currently selected head. nHS3– is the most significant bit. For
ATA Interface Reference Manual, Rev. C 17