Specifications

Hardware Description of LCN Node Processors – CLCN A/B I/O Board (or LCN I/O Board)
34 Application ModuleX Service 12/01
Honeywell
3.4 CLCN A/B I/O Board (or LCN I/O Board)
Overview
This board provides the physical interface to the LCN cables. It is used
with both versions of node processors (K2LCN/K4LCN and HMPU).
LCN address
pinning
The A
X
M LCN address pinning feature for defining the LCN physical
node number is located on this board. These address jumpers must be
properly configured at the time of hardware installation.
See the Five/Ten-Slot Service manual for additional pinning
details.Reference: >> LCN I/O Pinning (Section 2.8)
CAUTION
Conflict in pinning possible—The K2LCN (or K4LCN)
processor board has a duplicate LCN node pinning feature.
The address jumpers on the K2LCN/K4LCN must all be
removed when it is used in conjunction with an CLCN A/B I/O
(or LCN I/O) board.
The LCN node address pinning on a LCN I/O board is illustrated in the
diagram below. The pinning is identical on the CLCN A/B board.
40027
The 1 and 0 refer to DIP switch positions when
a switch assembly is installed in place of the
jumper block.
Sample is 43
Jumper Out = 1
Jumper In = 0
10
Not on Board
01
2
3
4
56P
LCN Address
Binary
Weight
PARITY
64
32
16
8
4
2
1
The overall number of jumpers out, including
the parity jumper, must be an odd number.
Note that addresses 0-127 could be set, but
software will allow only node addresses 1-64.
CLCN A/B I/O
Board