Specifications

Hardware Description of LCN Node Processors – K4LCN-X Node Processor
26 Application ModuleX Service 12/01
Honeywell
K4LCN Pinning
The K4LCN board has an LCN node number pinning feature on the
board itself. This feature is duplicated on the CLCN A/B I/O or LCN I/O
board that is installed directly behind the K4LCN board in the AXM
Five-Slot Module chassis.
ATTENTION
The address pinning jumpers must all be removed from the
K4LCN board when it is used in conjunction with a CLCN
A/B I/O (or LCN I/O) board. The node number pinning must be
done on the CLCN A/B I/O (or LCN I/O) board in this case.
The following illustration shows the LCN address pinning for a K4LCN
board when used in the A
X
M’s Five-Slot Module chassis.The illustration
shows the location of the pinning block, TS2, on the early production
K4LCN board, assembly 51401946-100.
LCN Address
Pinning
NOT ON BOARD
PARITY
64
32
16
8
4
2
1
10
01
2
3
45
6
P
LCN ADDRESS
BINARY
WEIGHT
52585-A
The pinning requirements are the same for the latest production K4LCN
board, assembly 51402755-100. Refer to the previous illustration of the
board’s assembly layout for the approximate location of the pinning block,
TS1.