Specifications

Hardware Description of LCN Node Processors
3.3 CLCN A/B I/O (or LCN I/O) Board
3/96 Application Module
X
Service 21
Honeywell Inc.
3.3 CLCN A/B I/O (or LCN I/O) Board
Overview
This board provides the physical interface to the LCN cables. It is used
with both versions of node processors (K2LCN and HMPU).
LCN address
pinning
The A
X
M LCN address pinning feature for defining the LCN physical node
number is located on this board. These address jumpers must be properly
configured at the time of hardware installation.
See the Five/Ten-Slot service manual for additional pinning details.
The LCN node address pinning is illustrated in the diagram below.
CAUTION
Conflict in pinning possible—
The K2LCN processor
board has a duplicate LCN node pinning feature. The
address jumpers on the K2LCN must all be removed
when it is used in conjunction with an CLCN A/B I/O
(or LCN I/O) board.
40027
The 1 and 0 refer to DIP switch positions when
a switch assembly is installed in place of the
jumper block.
Sample is 43
Jumper Out = 1
Jumper In = 0
10
Not on Board
012 34 56P
LCN Address
Binary
Weight
PARITY
64
32
16
8
4
2
1
The overall number of jumpers out, including
the parity jumper, must be an odd number.
Note that addresses 0-127 could be set, but
software will allow only node addresses 1-64.
CLCN A/B I/O
Board