Computer Drive User Manual

Cheetah NS 10K.2 FC Product Manual, Rev. B 17
The Pass-through state is disabled while the drive performs self test of the FC interface. The control line for an
external port bypass circuit remains in the Enable Bypass state while self test is running. If the bypass circuit is
present, loop operation may continue. If the bypass circuit is not present, loop operation will be halted while the
self test of the FC interface runs.
When the self test completes successfully, the control line to the bypass circuit is disabled and the drive enters
the FC-AL Initializing state. The receiver on the next device in the loop must synchronize to output of the newly
inserted drive.
If the self-test fails, the control line to the bypass circuit remains in the Enable Bypass state.
Note. It is the responsibility of the systems integrator to assure that no temperature, energy, voltage haz-
ard, or ESD potential hazard is presented during the hot connect/disconnect operation. Discharge
the static electricity from the drive carrier prior to inserting it into the system.
Caution. The drive motor must come to a complete stop prior to changing the plane of operation. This time is
required to insure data integrity.
5.2.4 S.M.A.R.T.
S.M.A.R.T. is an acronym for Self-Monitoring Analysis and Reporting Technology. This technology is intended
to recognize conditions that indicate imminent drive failure and is designed to provide sufficient warning of a
failure to allow you to back up the data before an actual failure occurs.
Note. The drive’s firmware monitors specific attributes for degradation over time but can’t predict instanta-
neous drive failures.
Each monitored attribute has been selected to monitor a specific set of failure conditions in the operating per-
formance of the drive and the thresholds are optimized to minimize “false” and “failed” predictions.
Controlling S.M.A.R.T.
The operating mode of S.M.A.R.T. is controlled by the DEXCPT and PERF bits on the Informational Exceptions
Control mode page (1Ch). Use the DEXCPT bit to enable or disable the S.M.A.R.T. feature. Setting the DEX-
CPT bit disables all S.M.A.R.T. functions. When enabled, S.M.A.R.T. collects on-line data as the drive performs
normal read and write operations. When the PERF bit is set, the drive is considered to be in “On-line Mode
Only” and will not perform off-line functions.
You can measure off-line attributes and force the drive to save the data by using the Rezero Unit command.
Forcing S.M.A.R.T. resets the timer so that the next scheduled interrupt is in two hours.
You can interrogate the drive through the host to determine the time remaining before the next scheduled mea-
surement and data logging process occurs. To accomplish this, issue a Log Sense command to log page 0x3E.
This allows you to control when S.M.A.R.T. interruptions occur. Forcing S.M.A.R.T. with the RTZ command
resets the timer.
Performance impact
S.M.A.R.T. attribute data is saved to the disk so that the events that caused a predictive failure can be recre-
ated. The drive measures and saves parameters once every two hours subject to an idle period on the FC-AL
bus. The process of measuring off-line attribute data and saving data to the disk is uninterruptable. The maxi-
mum on-line only processing delay is summarized below:
Maximum processing delay
On-line only delay
DEXCPT = 0, PERF = 1
Fully-enabled delay
DEXCPT = 0, PERF = 0
S.M.A.R.T. delay times
42 milliseconds
163 milliseconds