Instruction manual

Memory Configuration Logic
This logic circuit creates the chip select signals for the ROM and RAM chips, depending on the configuration (see the Memory ICs and
Configuration Flip-flop schematic) and the address requested. It is implemented with two-input logic gates and inverters on the 9 ICs that
take up most of the room on the circuit board. The logic performs the following calculation (the CS signals are all active-low, that is, are
logical 0 or GND when asserted):
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