Instruction manual

signals, with +5V and ground power lines, are brought to the disk and memory board through the P1 and P2 connectors. The data and control
lines are passed to the serial interface through the P4 connector. Note the bit of logic with inputs from A1 to A3, with the outputs Add 2 or 3,
and Add 0 or 1. This logic was needed because the serial interface board has minimal chip select logic on it, and will be activated for any
input/output request for port addresses with A1 = 1. The Add 2 or 3 is sent to the serial interface connector P5 in the place of A1, so now
other addresses that have A1 = 1, such as 10, 11, 14, and 15, can be used for the disk interface. The Add 0 or 1 is passed to the memory
configuration selection flip flop, seen below.
The IDE interface consists of TTL level signals sent to and from a series of input/output ports. The disk interface is selected when A3 = 1,
and I/O_Req is asserted. Address lines A0 through A2 determine which IDE interface register is selected for reading/writing. The IDE
connector (labeled PATA_CONN in the schematic) can be connected directly to the system data bus, because it has three-state outputs. Here,
data bits 0 to 7 are connected, and bits 8 to 15 are grounded through 1K resistors. This means for disks running in 16-bit mode half the data
is not retrievable, a trade-off to make the hardware simpler.
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