Specifications

©Copyright 2001-2013 SD Group (Panasonic, SanDisk, Toshiba) and SD Card Association
Physical Layer Simplified Specification Version 4.10
181
CMD19
A new command for sending tuning block
DAT or DAT[3:0]
4-bit data line of SD bus
DDR
Double data rate signaling
DDR50
One of UHS modes with double data rate. Up to 50MB/sec at 50MHz
DS
Default Speed Mode
DSR
Driver Stage Register
ECC
Error Correction Code
eSD
Embedded SD Memory Device defined by Part 1 eSD Addendum
ESL
Equivalent Series Inductance
ESR
Equivalent Series Resistance
FD156
UHS-II Full Duplex mode with data transfer rate up to 156MB/s
HD312
UHS-II Half Duplex with 2 Lanes mode with data transfer rate up to 312MB/s
Host-SDR-FD
One of host types with SDR signaling, fixed-delay (can't use tuning)
Host-SDR-VD
One of host types with SDR signaling, variable-delay (can use tuning)
Host-DDR
One of host types with DDR signaling
HS
High Speed Mode
LOW, HIGH
Binary interface states with defined assignment to a voltage level
MSB, LSB
The Most Significant Bit or Least Significant Bit
MLCC
Multi-Layer Ceramic Capacitor
MTP
Multiple Time Programmable memory
N
ERASE
The recommended numbers of AUs to be erased in one erase operation.
T
ERASE
Timeout value used for erasing multiple AU's as specified by ERASE_SIZE.
T
OFFSET
Offset time used for calculating erase timeout.
NSAC
Defines the worst case for the clock rate dependent factor of the data access
time
OCR
Operation Conditions Register
OTP
One Time Programmable memory
P
w
Performance of Write
P
m
Performance of Move
P
r
Performance of Read
PDN
Power Delivery Network
RCA
Relative Card Address register
ROM
Read Only Memory
RU
Recording Unit
SDCLK
Clock line of SD bus
S18R
Switching to 1.8V Request in ACMD41 argument
S18A
Switching to 1.8V Accepted in ACMD41 response
SPI
Serial Peripheral Interface
TAAC
Defines the time dependent factor of the data access time
tag
Marker used to select groups or sector to erase
TBD
To Be Determined (in the future)
T
fw
FAT write time
T
fr
FAT read time
t
ODLY
Output Delay from SDCLK under all delay parameters condition.
UHS
Ultra High Speed
UI
Unit Interval is one bit nominal time, SDCLK nominal period.
SD Bus I/F
Interface using contact pin numbers 1 to 9.
SDR
Single data rate signaling
SDR12
One of UHS-I modes with single data rate. Up to 12.5MB/sec at 25MHz
SDR25
One of UHS-I modes with single data rate. Up to 25MB/sec at 50MHz
SDR50
One of UHS-I modes with single data rate. Up to 50MB/sec at 100MHz
SDR104
One of UHS-I modes with single data rate. Up to 104MB/sec at 208MHz
UHS50
One of UHS-I Card Types supporting SDR50