Specifications

©Copyright 2001-2013 SD Group (Panasonic, SanDisk, Toshiba) and SD Card Association
Physical Layer Simplified Specification Version 4.10
153
7. SPI Mode
7.1 Introduction
The SPI mode consists of a secondary communication protocol that is offered by Flash-based SD
Memory Cards. This mode is a subset of the SD Memory Card protocol, designed to communicate with
a SPI channel, commonly found in Motorola's (and lately a few other vendors') microcontrollers. The
interface is selected during the first reset command after power up (CMD0) and cannot be changed
once the part is powered on.
The SPI standard defines the physical link only, and not the complete data transfer protocol. The SD
Memory Card SPI implementation uses a subset of the SD Memory Card protocol and command set.
The advantage of the SPI mode is the capability of using an off-the-shelf host, hence reducing the
design-in effort to minimum. The disadvantage is the loss of performance of the SPI mode versus SD
mode (e.g. Single data line and hardware CS signal per card).
The commands and functions in SD mode defined after the Version 2.00 are not supported in
SPI mode. The card may respond to the commands and functions even if the card is in SPI
mode but host should not use them in SPI mode.
7.2 SPI Bus Protocol
While the SD Memory Card channel is based on command and data bit streams that are initiated by a
start bit and terminated by a stop bit, the SPI channel is byte oriented. Every command or data block is
built of 8-bit bytes and is byte aligned to the CS signal (i.e. the length is a multiple of 8 clock cycles).
The card starts to count SPI bus clock cycle at the assertion of the CS signal. Every command or data
token shall be aligned to 8-clock cycle boundary.
Similar to the SD Memory Card protocol, the SPI messages consist of command, response and data-
block tokens. All communication between host and cards is controlled by the host (master). The host
starts every bus transaction by asserting the CS signal low.
The selected card always responds to the command as opposed to the SD mode.
When the card encounters a data retrieval problem in a read operation, it will respond with an error
response (which replaces the expected data block) rather than by a timeout as in the SD mode.
Additionally, every data block sent to the card during write operations will be responded with a data
response token.
In the case of a Standard Capacity Memory Card, a data block can be as big as one card write block
and as small as a single byte. Partial block read/write operations are enabled by card options specified
in the CSD register.
In case of
SDHC and SDXC Cards, block length is fixed to 512 bytes. The block length set by CMD16 is
only used for CMD42 and not used for memory data transfer. So, partial block read/write operations are
also disabled. Furthermore, Write Protected commands (CMD28, CMD29 and CMD30) are not
supported.