Specifications

©Copyright 2001-2013 SD Group (Panasonic, SanDisk, Toshiba) and SD Card Association
Physical Layer Simplified Specification Version 4.10
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Figure 4-29: A Blank in the Simplified Specification ....................................................................................... 92
Figure 4-30 : A Blank in the Simplified Specification ...................................................................................... 92
Figure 4-31: A Blank in the Simplified Specification ....................................................................................... 92
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Figure 4-33: A Blank in the Simplified Specification ....................................................................................... 92
Figure 4-34: A Blank in the Simplified Specification ....................................................................................... 92
Figure 4-35: A Blank in the Simplified Specification ....................................................................................... 92
Figure 4-36: A Blank in the Simplified Specification ....................................................................................... 92
Figure 4-37 : A Blank in the Simplified Specification ...................................................................................... 92
Figure 4-38 : A Blank in the Simplified Specification ...................................................................................... 92
Figure 4-39 : A Blank in the Simplified Specification ...................................................................................... 92
Figure 4-40 : A Blank in the Simplified Specification ...................................................................................... 92
Figure 4-41 : A Blank in the Simplified Specification ...................................................................................... 92
Figure 4-42 : A Blank in the Simplified Specification ...................................................................................... 92
Figure 4-43 : A Blank in the Simplified Specification ...................................................................................... 92
Figure 4-44 : A Blank in the Simplified Specification ...................................................................................... 92
Figure 4-45 : Timing of Single Block Read Command in DDR50 Mode ........................................................ 92
Figure 4-46: Overview of Speed Class Specification ..................................................................................... 93
Figure 4-47: Definition of Allocation Unit (AU) ............................................................................................... 93
Figure 4-48 : Example of Writing Fragmented AU ......................................................................................... 94
Figure 4-49: Card Performances between 16 RUs ........................................................................................ 95
Figure 4-50: Three Performance Curves ....................................................................................................... 97
Figure 4-51: Typical Sequence of FAT Update .............................................................................................. 97
Figure 4-52 : Measurement of Pw (AU size is larger than 4MB) ................................................................. 101
Figure 4-53 : Definition of CMD20................................................................................................................ 103
Figure 4-54 : Definition of CMD20................................................................................................................ 103
Figure 4-55 : Example of Speed Class Recording ....................................................................................... 105
Figure 4-56: Example Erase Characteristics (Case 1 TOFFSET=0) ........................................................... 108
Figure 4-57: Example Erase Characteristics (Case 2 TOFFSET=2) ........................................................... 109
Figure 4-58 : Set Block Count Command .................................................................................................... 110
Figure 5-1: ERASE_BLK_EN = 0 Example ................................................................................................. 119
Figure 5-2: ERASE_BLK_EN = 1 Example ................................................................................................. 119
Figure 5-3 : Extension Register Space ........................................................................................................ 129
Figure 5-4 : Read Extension Register Single Block Command (CMD48) ................................................... 130
Figure 5-5 : Extension Register Read Operation by CMD48 ....................................................................... 131
Figure 5-6 : Data Port Read Operation by CMD48 ...................................................................................... 131
Figure 5-7 : Write Extension Register Single Block Command (CMD49) ................................................... 132
Figure 5-8 : Extension Register Write Operation by CMD49 ....................................................................... 133
Figure 5-9 : Data Port Write Operation by CMD49 ...................................................................................... 134
Figure 5-10 : Read Extension Register Multi-Block Command (CMD58) ................................................... 135
Figure 5-11 : Extension Register and Data Port Read Operation by CMD58 ............................................. 135
Figure 5-12 : Write Extension Register Multi-Block Command (CMD59) .................................................... 136
Figure 5-13 : Extension Register and Data Port Write Operation by CMD59 ............................................. 136
Figure 5-14 : General Information for Memory ............................................................................................ 138
Figure 5-15 : Data Structure of General Information ................................................................................... 139
Figure 5-16 : Power Management Revision Register .................................................................................. 143
Figure 5-17 : Power Management Status Register ...................................................................................... 143
Figure 5-18 : Power Management Setting Register ..................................................................................... 144
Figure 5-19 : Power Off Notification Flow .................................................................................................... 144
Figure 5-20 : Power Sustenance Enabling / Disabling Sequence Flow ...................................................... 145
Figure 5-21 : Power Down Mode Entering / Exiting Sequence Flow ........................................................... 147
Figure 6-1: Bus Circuitry Diagram ................................................................................................................ 148
Figure 6-2: A Blank in the Simplified Specification ....................................................................................... 148