User manual

Appendix
ComTec GmbH 7-13
have something to do with the latency in the block transfers through the PCI bus. Is this correct? Can you
explain this more for me? What are the limiting factors? This is important because all of our applications
involve random (Poisson) arrival statistics for data. I am trying to "de-rate" the various performance
numbers to predict what will happen for random arrival data, and this is not straightforward given the
numbers shown. Usually the difference is at least a 3X reduction for a reasonable dead time loss, but it
isn't clear what to do in this case.
A: 3) We are actually looking at the data storage rate which is from the FIFO via the PCI bus to RAM (in
this case because we do not have a RAID which might be even faster). At this point the data is
transferred in block form. Your point would be quite valid if the input of the MPA-3 would be the restriction
- however the input of the MPA-3 is much faster in accepting data than can actually be transferred. If the
ADCs used are fast enough for the data acceptance capability of the MPA-3 any random data arriving will
be derandomized in the FIFO. Any dead time is therefore negligible because the average will be the
same as for periodic input signals. I hope you can see that the data transfer performance of the MPA-3
does not depend on periodic or randomly arriving events on the input side but on the capability of the
PCI-bus and the selected storage device. Rather than "de-rating" the MPA-3 performance attention
should be given to selecting the right frontend- and storage devices to match the requirements of the
application.
3) Here I would like to give you some more detailed technical information: The data transfer works the
following way:
During an acquisition two seperated threads are running initiated by the MPA3 server program: the DMA
handling thread and the evaluation thread. The DMA handling thread always calls the driver by providing
a RAM buffer of specified size (the buffer size can be specified in the mpa3.ini file by a line blocksize=...
and can be rather large). The PCI board transferes any data coming in directly with DMA into the PC
RAM using an interrupt. When the driver call returns, the DMA handling thread in the software signals the
evaluation thread that there is a new buffer available and starts a new driver call specifying another buffer
(always two buffers are used alternatively).
The evaluation thread optionally dumps the data to disk (the speed is dependent on the harddisk used)
and evaluates it for histogramming. It must be ready with the evaluation of the last buffer before he can
start evaluating a new buffer. So you see the way how the FIFO size is involved and how a dual
processor system can help. Most of the time the data is transfered via DMA directly into the PC RAM. But
when the driver call returns, we are a short time in USER mode before a new driver call is initiated.
During this time the FIFO is filled with data and with the standard FIFO size of 1 k (actually only 512
double words are usable) it can then happen that the FIFO is full and the data stream stops for a short
time. In a dual processor system the second processor can work on evaluating the data and painting the
histogrammed spectra without perturbing the data flow and so reduces the probability of a full FIFO
during two DMA transfers.
The throughput rate numbers were taken by observing the FIFO full flag and are limits of a "throughput
without loss". For statistical data a rare loss of data normally can be accepted without problem; it just
increases a little bit the dead time of the system that you have any way in the ADC's but does not
influence the quality of the data. But for some experiments no dead time at all is acceptable and data are
coming with a continuous high rate. If the data come in small bursts, this is no problem because this can
be handled by a large DMA buffer size and, eventually, FIFO size. So the peak rate in a random flow can
be even much higher than the rates in our list without causing much problems.
7.6.2. Coincidence Definition Window
Q: We do not understand for what "move" button (move ADC registered in Coinc. with any) to Dependent
coinc. groups) is. Is there no problem even if an ADC is not registered in Coinc. with any? We understand
what "copy" button is for. However, we do not know how we should use "move" button. Please advise.
A: If an ADC is in the 'Coincidence with any' group, it means that an event is registered when this ADC
has a valid conversion.
If an ADC is in any 'Dependent coinc. group' it means that an event is registered when all ADC's in this
group have valid conversions.