Specifications

Analog Output Modules
364
31007715 6/2008
Output
Status Registers
The I/O status process image is located in a reserved block of 4096 16-bit registers
(registers 45 392 through 49 487) that represent the status of all the I/O modules
(along with the data for the input modules) on the island bus.
The six LSBs in each register represent the status of each output channel:
1 Bit 0 represents global status (GS). It has a value of 0 when no errors are detected. It has
a value of 1 when bit 1 has a value of 1.
2 Bit 1 represents the status of PDM voltage on the island’s actuator bus. It has a value of 1
when the PDM is powered. A PDM error turns on the GS bit (bit 0).).
3 Bit 2 represents the presence or absence of an OVW. An OVW does not turn on the GS
bit (bit 0).
4 Bit 3 represents the presence or absence of an OVE. An OVE does not turn on the GS bit
(bit 0).
5 Bit 4 represents the presence or absence of a UVW. An UVW does not turn on the GS bit
(bit 0).
6 Bit 5 represents the presence or absence of a UVE. An UVE does not turn on the GS bit
(bit 0).
Note: The detection of error conditions on the PDM output power connection may
be delayed by as much as 15 ms from the event, depending on the sensor bus
load, the system configuration and the nature of the fault.
Field power faults that are local to the output module are reported immediately.
STB AVO 0200 Status Register Format
always set to 0
67
1
23
4
5
0
1415
9
10
11
1213
8
not used;
GS (see 1)
PDM (see 2)
OVW (see 3)
OVE (see 4)
VW (see 5)
UVE (see 6)
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