Specifications

Analog Input Modules
242
31007715 6/2008
Status
Byte Structure
The second, fourth, sixth, and eighth registers in the module's input process image
are the status words. The STB AVI 0300 can detect and report voltage overflow
conditions, as well as other errors.
The eight least significant bits (LSB) in each register represent the status of each
input channel:
1 Bit 0 is the global status (GS) bit for the input channel. It has a value of 0 when no errors
are detected. It has a value of 1 when bit 1 and/or bit 3 and/or bit 5 and/or bit 7 have a value
of 1.
2 Bit 1 represents the status of the PDM voltage on the island’s sensor bus. It has a value of
0 when no PDM voltage errors are detected. A PDM error turns on the GS bit (bit 0).
3 Bit 2 represents the presence or absence of an OVW. An OVW does not turn on the GS
bit (bit 0).
4 Bit 3 represents the presence or absence of an OVE.An OVE turns on the GS bit (bit 0).
5 Bit 4 represents the presence or absence of a UVW. An UVW does not turn on the GS bit
(bit 0).
6 Bit 5 represents the presence or absence of a UVE. A UVE turns on the GS bit (bit 0) when
the voltage range is +/-10 VDC or +/-5 VDC; a UVE does not turn on the GS bit (bit 0) when
the voltage range is 0 to 5 VDC, 0 to 10 VDC, or +1 to 5 VDC.
7 Bit 6 not used; always 0.
8 Bit 7 represents the presence or absence an internal communication error (ICE). This error
turns on the GS bit (bit 0).
Note: When the GS bit is on, the channel data value may not be valid.
Note: The detection of error conditions on the PDM input power connection may
be delayed by as much as 15 ms from the event, depending on the sensor bus
load, the system configuration, and the nature of the fault.
Field power faults that are local to the input module are reported immediately.
STB AVI 0300 Status Register Format
always set to 0
67
1
23
4
5
0
1415
9
10
111213
8
not used;
GS (see 1)
PDM (see 2)
OVW (see 3)
OVE (see 4)
UVW (see 5)
UVE (see 6)
0(see7)
ICE (see 8)
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