Specifications

Analog Input Modules
236
31007715 6/2008
Data
Word Structure
The first, third, fifth, and seventh registers in the module's input process image are
the data words. Each register represents the input current of a channel in the IEC
data format. The data has 15-bit + sign resolution. The bit structure in each data
register is as follows:
All 16 bits in each data word are significant. They allow you to represent analog input
voltages with all the integer values ranging from -32 768 to +32 767.
For the 1 to 5 VDC, 0 to 5 VDC, and 0 to 10 VDC operating ranges, the sign bit (bit
15) is always 0, indicating that negative voltage values are not read.
Data Formats for 1 to 5 VDC and 0 to 5 VDC:
In an ideal linear voltage representation for +1 to 5 VDC range (one with the default
offset or max count settings (see p. 228)), a value of 32 001 represents an OVW. If
the input value is less than or equal to -1, the module reports a UVW. When the input
value reaches 32 767, an OVE occurs. When the input value reaches -767, a UVE
occurs.
Note: Errors and warnings are based on count values, not physical values. The
current values in the tables below are ideal values.
Error +1 to 5 VDC Range 0 to 5 VDC Range
OVE (over voltage error) 5.10 VDC
(32 767)
5.12 VDC
(32 767)
OVW (over voltage warning) >5 VDC
(32 001)
>5 VDC
(32 001)
UVW (under voltage warning) <1 VDC
(-1)
<0.12 VDC
(767)
UVE (under voltage error) <0.91 VDC
(-767)
0 VDC
(0)
2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
sign
8
0
STB AVI 0300 Data Register Format
12
3
4
5
6
7
910111213
14
15
2
2
2
1
2
0
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