Specifications

Analog Input Modules
192
31007715 6/2008
Status
Byte Structure
The second, fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth registers
in the module's input process image are the status words. The STB ACI 1400 can
detect and report current overflow conditions.
The eight least significant bits (LSB) in each register represent the status of each
input channel:
1 Bit 0 represents global status (GS). It has a value of 0 when no errors are detected. It has
a value of 1 when bit 1 and/or bit 3 and/or bit 6 and/or bit 7 has a value of 1.
2 Bit 1 represents the status of the PDM voltage on the island’s sensor bus. It has a value of
1 when PDM error has been detected. A PDM error turns on the GS bit (bit 0).
3 Bit 2 represents the presence or absence of an OCW. An OCW does not turn on the GS
bit (bit 0).
4 Bit 3 represents the presence or absence of an OCE. An OCE turns on the GS bit (bit 0).
5 Bit 4 represents the presence or absence of a UCW. A UCW does not turn on the GS bit
(bit 0).
6 Bit 5 represents the presence or absence of a UCE. A UCE does not turn on the GS bit (bit
0).
7 Bit 6 represents the presence or absence of a broken wire error (BWE). A BWE turns on
the GS bit (bit 0). Valid only in the 4 to 20 mA range.
8 Bit 7 represents an internal communications error (ICE). This error turns on the GS bit
(bit 0).
Note: When the global status bit is on, the channel data value may not be valid.
Note: The detection of error conditions on the PDM input power connection may
be delayed by as much as 15 ms from the event, depending on the sensor bus
load, the system configuration and the nature of the fault.
Field power faults that are local to the input module are reported immediately.
STB ACI 1400 Status Register Format
always set to 0
not used;
ICE (see 8)
BWE (see 7)
UCE (see 6)
UCW (see 5)
OCE (see 4)
OCW (see 3)
PDM (see 2
GS (see 1)
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