Data Sheet

Time
DEBUG_CLK
P2_2
DEBUG_DATA
(to CC2541)
P2_1
DEBUG_DATA
(from CC2541)
P2_1
t
6
t
8
t
7
RESET_N
Time
DEBUG_CLK
P2_2
t
3
t
4
t
5
T0437-01
CC2541
www.ti.com
SWRS110D JANUARY 2012REVISED JUNE 2013
Figure 6. Debug Enable Timing
Figure 7. Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
T
A
= –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Synchronizers determine the shortest input pulse that can be
Input capture pulse duration recognized. The synchronizers operate at the current system 1.5 t
SYSCLK
clock rate (16 MHz or 32 MHz).
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