Schematics

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOTE:
Using bit swapping for DATA bus to allow easy pcb routing.
When using data bit swapping the low order bit of each
byte must reside at bit 0 of the byte. The remaining 7 data
bits can be swapped freely. This restriction is for write
leveling calibration.
Example D0 to D0 or D0 to D8, and D1-7 can be swapped.
When swapping byte lanes on 16-bit memories, remember
to move the DQMx, DQSx, and DQSx_B signals for that byte
lane.
4xDDR3
󰎷
󰎷󰎷
󰎷


󰎷
󰎷󰎷
󰎷












DDR3
VREF
DRAM_D0
DRAM_D1
DRAM_D2
DRAM_D3
DRAM_D4
DRAM_D5
DRAM_D6
DRAM_D7
DRAM_DQS0
DRAM_DQSN0
DRAM_DQM0
DRAM_D8
DRAM_D9
DRAM_D10
DRAM_D11
DRAM_D12
DRAM_D13
DRAM_D14
DRAM_D15
DRAM_DQS1
DRAM_DQSN1
DRAM_DQM1
DRAM_D16
DRAM_D17
DRAM_D18
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D22
DRAM_D23
DRAM_DQS2
DRAM_DQSN2
DRAM_DQM2
DRAM_D24
DRAM_D25
DRAM_D26
DRAM_D27
DRAM_D28
DRAM_D29
DRAM_D30
DRAM_D31
DRAM_DQS3
DRAM_DQSN3
DRAM_DQM3
DRAM_D32
DRAM_D33
DRAM_D34
DRAM_D35
DRAM_D36
DRAM_D37
DRAM_D38
DRAM_D39
DRAM_DQS4
DRAM_DQSN4
DRAM_DQM4
DRAM_D40
DRAM_D41
DRAM_D42
DRAM_D43
DRAM_D44
DRAM_D45
DRAM_D46
DRAM_D47
DRAM_DQS5
DRAM_DQSN5
DRAM_DQM5
DRAM_D48
DRAM_D49
DRAM_D50
DRAM_D51
DRAM_D52
DRAM_D53
DRAM_D54
DRAM_D55
DRAM_DQS6
DRAM_DQSN6
DRAM_DQM6
DRAM_D56
DRAM_D57
DRAM_D58
DRAM_D59
DRAM_D60
DRAM_D61
DRAM_D62
DRAM_D63
DRAM_DQS7
DRAM_DQSN7
DRAM_DQM7
DRAM_CKE1
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A15
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_CS0n
DRAM_RASn
DRAM_CASn
DRAM_W En
DRAM_ODT0
DRAM_CLK_P0
DRAM_CLK_N0
DRAM_CLK_P1
DRAM_CLK_N1
DRAM_CKE0
DRAM_RESET
DDR_A15
DRAM_A10
DRAM_A11
DRAM_D0
DRAM_D1
DRAM_D2
DRAM_D4
DRAM_D3
DRAM_D6
DRAM_D5
DRAM_D7
DRAM_D8
DRAM_D9
DRAM_D10
DRAM_D14
DRAM_D11
DRAM_D12
DRAM_D15
DRAM_D13
DRAM_DQS0
DRAM_DQSN0
DRAM_DQS1
DRAM_DQSN1
DRAM_A14
DRAM_CLK_P1
DRAM_CLK_N1
DRAM_CKE0
DRAM_CS0n
DRAM_DQM0
DRAM_DQM1
DRAM_A10
DRAM_A11
DRAM_A14
DRAM_CLK_P1
DRAM_CLK_N1
DRAM_CKE0
DRAM_CS0n
DRAM_DQM3
DRAM_DQM2
DRAM_ODT0
DRAM_RESET
DRAM_RASn
DRAM_CASn
DRAM_W En
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A12
DRAM_A13
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_ODT0
DRAM_RESET
DRAM_RASn
DRAM_CASn
DRAM_W En
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A12
DRAM_A13
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_A10
DRAM_A11
DRAM_A14
DRAM_CLK_P0
DRAM_CLK_N0
DRAM_CKE0
DRAM_CS0n
DRAM_DQM4
DRAM_DQM5
DRAM_ODT0
DRAM_RESET
DRAM_RASn
DRAM_CASn
DRAM_W En
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A12
DRAM_A13
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_A10
DRAM_A11
DRAM_A14
DRAM_CLK_P0
DRAM_CLK_N0
DRAM_CKE0
DRAM_CS0n
DRAM_DQM7
DRAM_DQM6
DRAM_ODT0
DRAM_RESET
DRAM_RASn
DRAM_CASn
DRAM_W En
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A12
DRAM_A13
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_A15 DRAM_A15
DRAM_A15
DRAM_A15
DRAM_D24
DRAM_D25
DRAM_D26
DRAM_D27
DRAM_D28
DRAM_D29
DRAM_D30
DRAM_D31
DRAM_D16
DRAM_D17
DRAM_D18
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D22
DRAM_D23
DRAM_DQS3
DRAM_DQSN3
DRAM_DQS2
DRAM_DQSN2
DRAM_D32
DRAM_D33
DRAM_D38
DRAM_D35
DRAM_D34
DRAM_D37
DRAM_D39
DRAM_D36
DRAM_D40
DRAM_D43
DRAM_D41
DRAM_D46
DRAM_D47
DRAM_D44
DRAM_D42
DRAM_D45
DRAM_DQS4
DRAM_DQSN4
DRAM_DQS5
DRAM_DQSN5
DRAM_D56
DRAM_D57
DRAM_D58
DRAM_D59
DRAM_D60
DRAM_D61
DRAM_D62
DRAM_D63
DRAM_D48
DRAM_D49
DRAM_D50
DRAM_D51
DRAM_D52
DRAM_D53
DRAM_D54
DRAM_D55
DRAM_DQS7
DRAM_DQSN7
DRAM_DQS6
DRAM_DQSN6
DDR_VREF
VDD_MEM1V5
GND
GND
GND
GND
DDR_VREF
GND
GND
VDD_MEM1V5
GND
DDR_VREFGND
GND
VDD_MEM1V5
GND
DDR_VREF
GND
VDD_MEM1V5
GND
DDR_VREF
GND
VDD_MEM1V5
VDD_MEM1V5
GND
GND
DDR_VREF
GND
VDD_MEM1V5
GND
GND
GND
GND
GND
VDD_MEM1V5
GND GND
DDR_VREF
Title
Size Document Number Rev
Date: Sheet of
<Doc> <RevCode>
<Title>
D
3 17Friday, July 24, 2015
Title
Size Document Number Rev
Date: Sheet of
<Doc> <RevCode>
<Title>
D
3 17Friday, July 24, 2015
Title
Size Document Number Rev
Date: Sheet of
<Doc> <RevCode>
<Title>
D
3 17Friday, July 24, 2015
C115
0.1uF
C130
0.1uF
C104
22uF/6.3V
C105
0.1uF
C140
22uF/6.3V
20%
.
C137
0.1uF
C114
0.1uF
C109
22uF/6.3V
C133
0.1uF
C121
0.1uF
R44
10K/1%
C113
0.1uF
C112
0.1uF
R46 33R
R42
240R/1%
C120
0.1uF
R50
240R/1%
2G_DDR3_SDRAM_256MX16
U14
MT41K128M16JT-12_K
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
A14
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
C103
0.1uF
C111
0.1uF
C134
0.1uF
C139
0.1uF
10%
.
C123
0.1uF
R80 0R
C136
0.1uF
R47
10K/1%
C129
0.1uF
C124
0.1uF
C108
0.1uF
C141
0.1uF
10%
.
C119
22uF/6.3V
C110
0.1uF
R45 10K/1%
2G_DDR3_SDRAM_256MX16
U13
MT41K128M16JT-12_K
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
A14
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
C135
0.1uF
C125
22uF/6.3V
C122
0.1uF
C127
0.1uF
R59
240R
.
1%
C118
0.1uF
R48
240R/1%
R49
240R/1%
C101
0.1uF
C131
0.1uF
C126
0.1uF
R60
240R
.
1%
C98
0.1uF
C100
0.1uF
C117
0.1uF
2G_DDR3_SDRAM_256MX16
U15
MT41K128M16JT-12_K
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
A14
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
C132
22uF/6.3V
C116
22uF/6.3V
2G_DDR3_SDRAM_256MX16
U12
MT41K128M16JT-12_K
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
BA0
M2
BA1
N8
BA2
M3
VDD1
B2
VDD2
D9
VDD3
G7
VDD4
K2
VDD5
K8
VDD6
N1
VDD7
N9
VDD8
R1
VDD9
R9
VDDQ1
A1
VDDQ2
A8
VDDQ3
C1
VDDQ4
C9
VSS1
A9
VSS2
B3
VSS3
E1
VSS4
G8
VSS5
J2
VSS6
J8
VSS7
M1
VSS8
M9
VSS9
P1
VSS10
P9
VSS11
T1
VSS12
T9
VSSQ1
B1
VSSQ2
B9
VSSQ3
D1
VSSQ4
D8
VSSQ5
E2
NC_L1
L1
NC_L9
L9
NC_M7
M7
A14
T7
DQ0
E3
DQ1
F7
DQ2
F2
DQ3
F8
DQ4
H3
DQ5
H8
DQ6
G2
DQ7
H7
A10/AP
L7
A11
R7
A12/BC
N7
LDQS
F3
LDQS
G3
UDQS
C7
UDQS
B7
DQ8
D7
DQ9
C3
DQ10
C8
DQ11
C2
DQ12
A7
DQ13
A2
DQ14
B8
DQ15
A3
VDDQ5
D2
VDDQ6
E9
VDDQ7
F1
VDDQ8
H2
VDDQ9
H9
VSSQ6
E8
VSSQ7
F9
VSSQ8
G1
VSSQ9
G9
A13
T3
NC_J9
J9
NC_J1
J1
CK
J7
CK
K7
CKE
K9
CS
L2
RAS
J3
CAS
K3
WE
L3
RESET
T2
ODT
K1
VREFCA
M8
VREFDQ
H1
ZQ
L8
LDM
E7
UDM
D3
C99
0.1uF
C107
0.1uF
C138
0.1uF
C102
22uF/6.3V
C128
0.1uF
R43
240R/1%
i.MX6Q - DDR
U8J
MCIMX6D5EYM10AD
DRAM_VREF
AC2
DRAM_D40
Y19
DRAM_D41
AB20
DRAM_D42
AB21
DRAM_D43
AD21
DRAM_D44
Y20
DRAM_D45
AA20
DRAM_D46
AE21
DRAM_D47
AC21
DRAM_SDQS5
AD20
DRAM_SDQS5
AE20
DRAM_DQM5
AC20
DRAM_D32
AA17
DRAM_D33
AA18
DRAM_D34
AC18
DRAM_D35
AE19
DRAM_D36
Y17
DRAM_D37
Y18
DRAM_D38
AB19
DRAM_D39
AC19
DRAM_DQM4
AB18
DRAM_SDQS4
AD18
DRAM_SDQS4
AE18
DRAM_D24
AE9
DRAM_D25
Y10
DRAM_D26
AE11
DRAM_D27
AB11
DRAM_D28
AC9
DRAM_D29
AD9
DRAM_SDQS3
AC10
DRAM_SDQS3
AB10
DRAM_D30
AD11
DRAM_D31
AC11
DRAM_DQM3
AE10
DRAM_D16
AB7
DRAM_D17
AA8
DRAM_D18
AB9
DRAM_D19
Y9
DRAM_D20
Y7
DRAM_D21
Y8
DRAM_D22
AC8
DRAM_SDQS2
AD8
DRAM_SDQS2
AE8
DRAM_D23
AA9
DRAM_DQM2
AB8
DRAM_A0
AC14
DRAM_A1
AB14
DRAM_A2
AA14
DRAM_A3
Y14
DRAM_A4
W14
DRAM_A5
AE13
DRAM_A6
AC13
DRAM_A7
Y13
DRAM_A8
AB13
DRAM_A9
AE12
DRAM_A10
AA15
DRAM_A11
AC12
DRAM_A12
AD12
DRAM_A13
AC17
DRAM_A14
AA12
DRAM_A15
Y12
ZQPAD
AE17
DRAM_CAS
AE16
DRAM_CS0
Y16
DRAM_CS1
AD17
DRAM_RAS
AB15
DRAM_RESET
Y6
DRAM_SDBA0
AC15
DRAM_SDBA1
Y15
DRAM_SDCLK_0
AD15
DRAM_SDCLK_0
AE15
DRAM_SDBA2
AB12
DRAM_SDCKE0
Y11
DRAM_SDCLK_1
AD14
DRAM_SDCLK_1
AE14
DRAM_SDCKE1
AA11
DRAM_SDODT0
AC16
DRAM_SDODT1
AB17
DRAM_SDWE
AB16
DRAM_D0
AD2
DRAM_D1
AE2
DRAM_D2
AC4
DRAM_D3
AA5
DRAM_D4
AC1
DRAM_D5
AD1
DRAM_SDQS0
AE3
DRAM_SDQS0
AD3
DRAM_D6
AB4
DRAM_D7
AE4
DRAM_DQM0
AC3
DRAM_D8
AD5
DRAM_D9
AE5
DRAM_D10
AA6
DRAM_D11
AE7
DRAM_D12
AB5
DRAM_D13
AC5
DRAM_D14
AB6
DRAM_SDQS1
AD6
DRAM_SDQS1
AE6
DRAM_D15
AC7
DRAM_DQM1
AC6
DRAM_D48
AC22
DRAM_D49
AE22
DRAM_D50
AE24
DRAM_D51
AC24
DRAM_D52
AB22
DRAM_D53
AC23
DRAM_D54
AD25
DRAM_D55
AC25
DRAM_SDQS6
AD23
DRAM_SDQS6
AE23
DRAM_DQM6
AD24
DRAM_D56
AB25
DRAM_SDQS7
AA25
DRAM_SDQS7
AA24
DRAM_D57
AA21
DRAM_D58
Y25
DRAM_D59
Y22
DRAM_D60
AB23
DRAM_DQM7
Y21
DRAM_D61
AA23
DRAM_D62
Y23
DRAM_D63
W25
NVCC_DRAM_8
V14
NVCC_DRAM_9
V15
NVCC_DRAM_10
V16
NVCC_DRAM_11
V17
NVCC_DRAM_12
V18
NVCC_DRAM_13
V9
NVCC_DRAM_1
R18
NVCC_DRAM_2
T18
NVCC_DRAM_3
U18
NVCC_DRAM_4
V10
NVCC_DRAM_5
V11
NVCC_DRAM_6
V12
NVCC_DRAM_7
V13
C106
0.1uF