Specifications

HighWire MTP-2 - 1.2, September 4, 2002 sbe_dprIoctl 125
DPR_SET_CLOCK_INFO. This command sets the current contents of selected
clocking registers in the T8102.
Arg points to a T8100_CLOCK_INFO.
DPR_DATA_ALIGNMENT. When there is a change in the Primary Clock, any data
subsequently transferred must be re-aligned to the new clock value. This
command determines the manner in which this re-alignment takes place.
Arg points to an integer containing one of the following data alignment values:
DPR_MODE. The mode of operation for the Time Slot Interchanger (TSI) can be
altered, and mode changes not requiring additional user parameters can be
invoked via this command. The mode changes that do not require additional
user parameters, aside from the base mode change parameters, are:
• Low-Latency (TTSI_LOWLAT)
• Frame-Integrity (TTSI_FRAMEI)
• Tri-State/High-Impedance (TTSI_TRISTATE)
T8100_PHASE_ALIGN_NONE The incoming frame is frequency locked to
an inbound frame, but not phase aligned.
T8100_PHASE_ALIGN_SNAP Instantaneous phase alignment at the
frame boundary.
T8100_PHASE_ALIGN_SLIDE A fraction of a bit time is removed from
each frame until sync is achieved.