Specifications

HighWire MTP-2 - 1.2, September 4, 2002 dprservice (7D) 109
DPR_GET_CLOCK_INFO. Retrieves the current contents of the selected clocking
registers in the T8102.
The putmsg control buffer is a structure of type dpr_ckin_t with the ckin_par
element a T8100_CLOCK_INFO structure that contains only the command.
The getmsg control buffer returned is also a dpr_ckin_t structure with the
error code in the ckin_err element, which is zero on success. In that case, the
clock information is in the ckin_par structure, which has the following
elements:
DPR_SET_CLOCK_INFO. Sets the values of the selected clocking registers in the
T8102.
The putmsg control buffer is a structure of type dpr_ckin_t. The ckin_par
element is a T8100_CLOCK_INFO structure that contains the values for the
T8102 clocking registers, as described in DPR_GET_CLOCK_INFO. The
getmsg control buffer returned is also a dpr_ckin_t structure with the error
code in the ckin_err element (zero on success).
DPR_DATA_ALIGNMENT. Sets the method to bring the data into alignment on a
clock change.
The putmsg control buffer is a structure of type dpr_usel_t with the usel_val
element the method for data alignment. The getmsg control buffer returned is
also a dpr_usel_t structure with the error code in the usel_err element, which
is zero on success. The data alignment methods are:
UINT8 ckm Master Clock Register
UINT8 ckn NETREF Selection Register
UINT8 ckp Programmable Outputs Register
UINT8 ckr Clock Resource Selection Register
UINT8 cks Secondary/Fallback Clock Register
UINT8 ck32 Local Clocks 2 and 3 Source Selection Register
UINT8 ckmd Local Clocks 0 and 1 Source Selection Register
UINT8 cknd Main Clock Source Divider Register
UINT8 ckrd Resource Divider Register
T8100_PHASE_ALIGN_NONE The incoming frame is frequency locked to
an inbound frame, but not phase aligned.
T8100_PHASE_ALIGN_SNAP Instantaneous phase alignment at the
frame boundary.
T8100_PHASE_ALIGN_SLIDE A fraction of a bit time is removed from
each frame until sync is achieved.