Specifications

HW400p/M Technical Reference - 1.0, March 6, 2002 CPLD Registers 43
Interrupt Source Register (ISR) The ISR is a 16-bit read-only register that is accessible by the MPC8245. The
16 interrupts are latched into this register and cleared when the interrupt has
been deasserted.
ISRA Interrupts.
Table 5-7 shows the interrupts assigned to ISRA.
Note: When any of the bits is a “1”, the corresponding interrupt is asserted.
Bits 7–4 are always “0” as they are not used on this product.
The ISRA interrupts are defined as:
ISRB Interrupts.
Table 5-8 shows the interrupts assigned to the ISRB locations 7
to 0.
The ISRB interrupts are defined as:
Note: Only INT2 and INT3 are asserted on the HW400p/M; all other bits are
always 0.
Table 5-7 Interrupt Source Register A – FFE20000
Bit 7–4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved INT11 INT10 INT9 INT8
INT11 PMC Site INTD Interrupt
INT10 PMC Site INTC Interrupt
INT9 PMC Site INTB Interrupt
INT8 PMC Site INTA Interrupt
Table 5-8 Interrupt Source Register B – FFE20001
Bit 7–4 Bit 3 Bit 2 Bit 1–0
Reserved IRREG3 IRREG2 Reserved
IRREG3 DUART_B Console
IRREG2 DUART_A Download