Specifications

34 Programming Information HW400p/M Technical Reference - 1.0, March 6, 2002
5. Programming Information
5-1. MPC8245 Memory Map
The MPC8245 local address space map is based on the Address Map B
template presented in the MPC8245 User’s Manual. The template imposes a
number of constraints on where a particular function can be located within
the MPC8245 memory space. Of particular concern to the HW400p/M design
is the size of the PCI master window, since both the local PCI resources and
the host system memory must be accessed through this region.
Master window The HW400p/M uses a 2GB master window, the largest window supported.
The MPC8245 dictates that a 2GB window must reside in the upper 2GB of
the MPC8245 address space, overlapping the reserved areas in the upper
48MB. These reserved areas show up as holes in the master window. That is,
an access to one of the reserved areas accesses the MPC8245 defined
function instead of PCI space.
8-bit peripheral devices The MPC8245 local address space map has the ability to address 8-bit
peripheral devices. Access to 8-bit devices is provided via the Port-X region. To
accommodate the five 8-bit devices on the HW400p/M, the 8-bit Port-X region
is externally decoded into two 512KB regions and sixteen 64KB regions. The
512KB regions are used to support the HW400p/M’s PLCC flash memory
devices and the 64KB regions are used to provide access to the EEPROM,
DUART, and CPLD.
16-bit peripheral devices The MPC8245 local address space map has the ability to address 16-bit
peripheral devices. Access to 16-bit devices is provided via the expanded
ROM interface.
Master PCI memory (MPCIM) The MPCIM region of the MPC8245’s address space maps 1:1 to the same
region on the HW400p/M’s local PCI bus. This arrangement was chosen to
simplify the overall HW400p/M design by reducing the number of address
translations required. Details of what is accessible via the MPC8245 MPCIM
region are contained in the HW400p/M local PCI bus address space map.
See Table 5-1.