Specifications

HW400p/M Technical Reference - 1.0, March 6, 2002 PCI–to-PCI Bridge 23
4-3. PCI–to-PCI Bridge
PCI interface The PCI bus interface is implemented using the Intel 21554 PCI/PCI
Translation Bridge chip operating at 33MHz on the backplane (PCI) and local
PCI bus interface. The 21554 is a PCI master or slave for memory, and I/O
accesses on a 33MHz/32- or 64-bit PCI bus. The secondary (local side) PCI
bus is 32 bits in width at 33MHz.
Local PCI bus The Intel 21554 provides the PCI bridge functions between the host PCI
interface and local PCI bus. The 21554 supports a secondary (local side) PCI
bus at a maximum operating frequency of 33MHz. The local PCI bus is 32-bit.
The MPC8245 provides local PCI bus arbitration. Table 4-1 defines the PCI
configuration access bits (IDSEL) used for each local PCI-capable component.
21554 initialization without serial
preload
The HW400p/M does not use serial ROM to initialize the 21554. After primary
reset, the 21554 terminates the serial ROM read if the first byte read does not
contain the preload enable sequence. The MPC8245 must initialize the
21554 registers.
Note: At power-up or PCI reset, the 21554 should be configured so that host
access to the local PCI bus is disabled until the host’s configuration cycle is
complete.
Table 4-1 PCI configuration access bit definitions
Local PCI IDSEL Address Bit MPC8245 REQ/GNT
Ethernet Controller 16 0
PCI Bridge – 21554 17 1
PMC site 20 2