Specifications

12 Specifications HW400p/M Technical Reference - 1.0, March 6, 2002
3-2. Memory
The HW400p/M contains a variety of memory devices for use by the
MPC8245. Their characteristics are described in the following sections.
Synchronous DRAM The synchronous DRAM provides the following features:
•133MHz operation
• 64MB organized as a single bank of four 8M x 16 devices
•No parity
Boot PROM The boot PROM provides the following features:
• The Flash implementation uses two byte-wide devices
• PLCC devices (29LV010 or 29LV040) socketed
• 3.3V LVTTL-compatible
• Attached to the local I/O bus of the MPC8245
• U65 and U66 PCB reference designators (U66 is accessed by processor
at power up)
EEPROM The EEPROM provides the following features:
• A 2k x 8 parallel device, used for the retention of manufacturing
identification information
• 250nsec
• Attached to the local I/O bus of the MPC8245
High-density Flash Two Intel 3V Advance+ Boot Block Flash devices are used, the
TE28F320C3B100A.
The optional high-density Flash provides the following features:
• 48-pin TSOP with an access time of 100nsec or better
• 0/2/4/8 Mbytes organized as 0/512KB/1MB/2MB x 16 bits