HW400p/M A High-Performance PCI Communications Controller Technical Reference, Rev. 1.0, March 6, 2002 Primary Text Number M8239 SBE, Inc. 2305 Camino Ramon #200, San Ramon, California 94583 (925) 355-2000 Technical Support (800) 444-0990 Fax: (925) 355-2020 FaxBack Service: (800) 214-4723 Website: http://www.sbei.
Copyright ©2002 by SBE, Inc. All rights reserved. No part of this manual may be reproduced by any means without written permission from SBE, Inc., except that the purchaser may copy necessary portions for internal use only. While every effort has been made to ensure the accuracy of this manual, SBE cannot be held responsible for damage resulting from information herein. All specifications are subject to change without notice. SBE, Inc. and the SBE logo are trademarks of SBE, Inc.
Contents 1. About This Manual ..................................................................................................................................... 7 1-1. Related Documents ..............................................................................................................................7 1-2. Documentation Conventions ................................................................................................................8 2. HW400p/M Introduction .........................
PCI interface .................................................................................................................................... 23 Local PCI bus ................................................................................................................................... 23 21554 initialization without serial preload ................................................................................... 23 4-4. LEDs ........................................................................
Figures Figure 2-1 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 HW400p/M functional block diagram.................................................................................................... 10 HW400p/M board layout......................................................................................................................... 11 HW400p/M dimensions ................................................................................................................
Tables Table 3-1 Table 3-2 Table 3-3 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 5-14 Table 5-15 Table 5-16 Operating requirements........................................................................................................................... 14 Power requirements............................................................
1. About This Manual This manual is the technical reference for the HW400p/M communications controller for the PCI bus. This manual is intended for hardware engineers who are incorporating the HW400p/M into a system. The HW400p/M Technical Reference includes: • Introduction and background on the HW400p/M communications controller and SBE, Inc. • Specifications and physical characteristics of the controller • Support information • Installation instructions • Programming information 1-1.
1-2. Documentation Conventions Registers Register bits are numbered starting with 0. Bit 0 is the least significant and bit 7 is the most significant bit of a byte. Unless otherwise noted, register bits that are identified as “unused” do not affect the function of the register, and, if read, yield no information. Signals When referring to a signal function in text, signal names do not indicate polarity, and the / is not used.
2. HW400p/M Introduction The HW400p/M is a member of SBE’s HighWire™ product line, a family of high-performance communications products. The HW400p/M is a network interface and protocol processing product with these characteristics: • PCI variable length form factor • A single PMC site • PCI 2.1 host interface • Architecture and software similarity with HW400 2-1.
Figure 2-1 HW400p/M functional block diagram Development/Debug LEDs Ports Optional DUART CPLD EEPROM Flash/OTP Flash ROM NVRAM SDRAM I/O Bus and Ctrls For Development Only LEDs 10BaseT/ Am79C973 PMC Connectors 100BaseTx Ethernet Jn1 and Jn2 MPC8245 Processor Controller RJ-45 Xfrmr Local/Secondary PCI Bus 21554 PCI-to-PCI Bridge Host/Primary PCI Bus Connector 10 HW400p/M Introduction HW400p/M Technical Reference - 1.
3. Specifications This chapter details the physical characteristics and specifications for the HW400p/M communications controller. Figure 3-1 shows the HW400p/M board layout. See Figure 2-1 for a HW400p/M functional block diagram. Figure 3-1 HW400p/M board layout RJ45 connector Debug connector Ethernet LEDS (4x) U65 J9 Dual-color U66 J8 Altera status LED CPLD EPM3256 MPC8245 AM79C973 JN2 JN1 21554 Intel PCI Bridge M2 M4 (3.3V) (5V) 3-1.
3-2. Memory The HW400p/M contains a variety of memory devices for use by the MPC8245. Their characteristics are described in the following sections. Synchronous DRAM The synchronous DRAM provides the following features: • 133MHz operation • 64MB organized as a single bank of four 8M x 16 devices • No parity Boot PROM The boot PROM provides the following features: • The Flash implementation uses two byte-wide devices • PLCC devices (29LV010 or 29LV040) socketed • 3.
3-3. I/O DUART 10/100 Mbps Ethernet/Am79C973 The Exar ST16C2550 Dual Universal Asynchronous Receiver/Transmitter (DUART) provides connectivity to the two serial ports via a console accessory kit. The Am79C973 controller is a single-chip 32-bit full-duplex, 10/100-Mbps fully integrated PCI-to-Wire Fast Ethernet controller.
3-4.
3-6. Physical Characteristics Table 3-3 provides the HW400p/M board’s parameters and dimensions. Table 3-3 HW400p/M physical characteristics Parameter Dimension Length 8.661 inches (22 cm) Height 4.25 inches (10.8 cm) Maximum component height (front) 0.570 inches (1.448 cm) Maximum component height (back) 0.105 inches (0.267 cm) Board thickness 0.062 inches ± 0.005 inches (0.157 cm ± 0.0127 cm) Figure 3-2 HW400p/M dimensions 8.661″ (22 cm) 4.25″ (10.8 cm) HW400p/M Technical Reference - 1.
3-7. Mean Time Between Failures The part failure source rate was calculated in accordance with the TELCORDIA TECHNOLOGIES Specification TR-332, version 6. This is based on an ambient temperature of 40 °C in a benign controlled environment, using Quality Level II parts. The mean time between failures for the HW400p/M is greater than or equal to 275,000 hours. 3-8.
Telecom CTR13 (includes CTR12 and ETS 300046; −2.048 Mbit/s structured 120 ohm) (Registration No. PENDING). FCC Part 68. This device was tested and found to comply with Part 68 of FCC Rules. A label can be found on the back of the board near the RJ45 connector. This label contains the FCC Registration Number for this unit. You must, upon request, provide this information to your telephone company. FCC Registration Number PENDING USOC Jack RJ48C Note: An FCC Modular Jack is provided with this equipment.
Industry Canada CS03 PENDING Note: The Industry Canada label identifies certified equipment. This certification means that the equipment meets telecommunications network protective, operational and safety requirements as prescribed in the appropriate Terminal Equipment Technical Requirements document(s). The Department does not guarantee the equipment will operate to the user’s satisfaction.
3-10. Software Support Contact SBE for a list of software available for the HW400p/M communications controller. SBE website – http://www.sbei.com SBE Technical Support – 1-800-444-0990 (in North America) SBE Technical Support – +925-355-2000 (outside North America) 3-11. Returns/Service Before returning any equipment for service, you must obtain a Return Material Authorization (RMA) number from SBE.
Specifications HW400p/M Technical Reference - 1.
4. Functional Information 4-1. MPC8245 Development/debug support Reset Development and debug support is provided in the console accessory kit. A COP header is also provided on board. See Section 4-9. The following types of reset are available on the MPC8245: • Power-on reset. • Host accessible reset, which allows the host on the PCI bus to reset only the board’s local bus. • External pushbutton reset via a special SBE reset/interrupt cable on the console accessory kit.
Figure 4-1 Voltage keying JN1 JN2 M2 M4 (3.3V) (5V) Figure 4-2 Voltage key post screw voltage key post Jn1/Jn2 side of PCB screw EMI requirements 22 Functional Information To ensure acceptable EMI performance, use a suitable EMI gasket on the installed PMC module. In addition, install all four mounting screws to provide proper grounding and mechanical stability. HW400p/M Technical Reference - 1.
4-3. PCI–to-PCI Bridge PCI interface The PCI bus interface is implemented using the Intel 21554 PCI/PCI Translation Bridge chip operating at 33MHz on the backplane (PCI) and local PCI bus interface. The 21554 is a PCI master or slave for memory, and I/O accesses on a 33MHz/32- or 64-bit PCI bus. The secondary (local side) PCI bus is 32 bits in width at 33MHz. Local PCI bus The Intel 21554 provides the PCI bridge functions between the host PCI interface and local PCI bus.
4-4. LEDs A dual-color board-status LED visible from the front panel of the HW400p/M PCI is controlled by the MPC8245 via the Board Status Register (BSR) in the CPLD. See Table 4-2 for a chart of the LED functions and physical descriptions. Figure 4-3 shows the board LEDs. Table 4-2 LEDs LED Function Qty Color Description Ethernet Ethernet Link Pass LED (LAN) 1 Green Controlled by the Am79C973 Ethernet controller; indicates an active link.
Figure 4-3 Board LEDs E th e rn e t L E D S (4 x ) R J4 5 c o n n e c to r D e b u g c o n n e c to r Dd e v e l o p m e n t L E D s J9 D u a l-c o lo r s ta tu s L E D J8 A lte r a C P L D E P M 3 2 5 6 A M 7 9 C 9 7 3 JN 1 HW400p/M Technical Reference - 1.
4-5. I/O Bus The I/O Bus connects the following functional elements: • DUART • EEPROM • Flash ROM • CPLD The I/O Bus has the following characteristics: • It is an 8/16-bit data bus. • It operates at 250-nsec cycle time buffered from the SDRAM bus. • It is the Port X bus from the MPC8245. DUART The DUART has two channels to support the console feature on channel B and the download feature on channel A. Each channel has a separate interrupt that is sent to the MPC8245 via the CPLD’s interrupt registers.
Flash ROM There are two types of Flash ROM on the HW400p/M: • Two contiguous 512-kByte banks for the Boot PROM. U66 is the lower bank while U65 is the upper bank. U66 is accessed by the MPC8245 upon power up or reset. • An optional 0/2/4/8 Mbytes of high-density Flash, comprised of two Intel 3V Advance+ Boot Block Flash devices organized as 0/512KB/1MB/2MB x 16 bits.
4-7. I/O Bus Control and Miscellaneous Logic Two Altera CPLD on the main board provide: • Port-X I/O bus controls signals and glue logic for all devices attached to the I/O bus • Control signals that drive the front panel LEDs • General-purpose I/O registers • Reset signals I/O registers The I/O registers are accessible only by the MPC8245. Table 4-4 identifies the I/O registers.
Power up and reset A microprocessor supervisory manager provides the power up reset. The device monitors both 3.3V and 2.0V levels and issues a reset if either voltage falls below its specification. The reset is active for 100ms. The reset generates other logical resets. This reset logic resides in the CPLD to provide system reset as the result of power up reset and pushbutton reset. The CPLD reset manages the various reset signals to all devices.
Table 4-6 PCI connector P1 pin assignments A 30 Functional Information B Pin Pin A B NC -12V 1 2 +12V NC NC GND 3 4 TDIa TDOa +5V +5V 5 6 +5V INTA# NC NC 7 8 +5V NC Reserved PRSNT1#b 9 10 V (I/O) Reserved Reserved PRSNT2#b 11 12 Keyway Keyway Keyway Keyway 13 14 Reserved Reserved RST# GND 15 16 V (I/O) CLK GNT# GND 17 18 GND REQ# Reserved V (I/O) 19 20 AD[30] AD[31] +3.
Table 4-6 PCI connector P1 pin assignments (continued) A B Pin Pin A B +3.3V AD[07] 53 54 AD[06] +3.
MPC8245 debug connector pin assignment.
4-9. COP (Common On-Chip Processor) Support The COP function on the MPC8245 processor allows a remote computer system to access and control the internal operations of the processor. The COP interface connects to the MPC8245 via its JTAG interface through the header J8. Jumper J9 must be installed to enable the COP function. Table 4-8 shows the COP header signal names and respective pin assignments.
5. Programming Information 5-1. MPC8245 Memory Map The MPC8245 local address space map is based on the Address Map B template presented in the MPC8245 User’s Manual. The template imposes a number of constraints on where a particular function can be located within the MPC8245 memory space. Of particular concern to the HW400p/M design is the size of the PCI master window, since both the local PCI resources and the host system memory must be accessed through this region.
HW400p/M Technical Reference - 1.0, March 6, 2002 Table 5-1 MPC8245 local address space memory map Start End MPC8245 Memory Map 35 Size Region 0x0000 0000 Description Reference 0x03FF FFFF 64MB CSDRAM MPC8245 SDRAM 0x0400 0000 0x77FF FFFF 1916MB RSVD Reserved 0x7800 0000 0x787F FFFF 8MB FLASH_C 0/1/4/8MB Extended Flash memory (Manufacturing option) 0x7880 0000 0x7FFF FFFF 120MB RSVD Reserved 0x8000 0000 0xFFEF FFFF 2015MB MPCIM PCI memory space master window.
5-2. Local PCI Address Space Map The local PCI bus address space is arbited by the MPC8245, which provides the IDSEL lines and performs the PCI configuration phase of the local PCI bus. Firmware Masters Unlike a standard PCI BIOS implementation, the MPC8245 firmware does not use a dynamic address map. The firmware uses static mapping because it knows of all possible PCI devices on the bus and their required window sizes. This simplifies the on board software by allowing static addressing to be used.
This space is also accessible by the multichannel DMA controller integrated into the MPC8245. Using the DMA controller, the MPC8245 can perform DMA operation using either its own memory or any of the resources on the local PCI bus as the source or destination. Table 5-3 shows the local PCI bus address space. Note: Large portions of the PCI address space map are reserved for possible future products based on the HW400p/M main board’s modular architecture. HW400p/M Technical Reference - 1.
Programming Information Table 5-3 Local PCI address space HW400p/M Technical Reference - 1.0, March 6, 2002 Start End Size Region Description 0x0000 0000 0x02FF FFFF 64MB KMEM MPC8245 Shared SDRAM in secondary PCI space. Also mapped into host PCI space. This is the host’s PCI bus window into the secondary PCI space. The mapping of this space onto the host PCI bus is a function of the 21554 PCI-to-PCI bridge.
5-3. High-Density Flash The HW400p/M supports up to 16 Mbytes of high-density Flash via the 8245’s Expanded ROM interface. This memory utilizes a 16-bit data bus. Bits in the General Purpose Register (see General Purpose Register (GPR) on page 49) provide information about the size of each device and number of devices. Bits NVSIZ[2:0] specifies the size of each device and bit NVDEV specifies the number of devices. Table 5-4 shows the various possibilities for the high-density Flash.
Table 5-4 High-density Flash Total Memory (Mbytes) Number of Devices NVDEV 1 1 0 8 Mbit, TE28F800C3BA110 000 0x7800 0000 0x780F FFFF 1 0 16 Mbit, TE28F160C3BA110 001 0x7800 0000 0x781F FFFF Device Size and Part Number NVSIZ [2:0] 8 Mbit, TE28F800C3BA110 2 2 1 000 8 Mbit, TE28F800C3BA110 1 0 2 1 1 0 16 Mbit, TE28F160C3BA110 64 Mbit, TE28F640C3BC100 2 2 1 Programming Information 0x7800 0000 0x783F FFFF 0x7800 0000 0x781F FFFF 001 011 010 0x7820 0000 0x783F FFFF 0x7800 0000
5-4. AMD Ethernet Controller Register Map For the Am79C973 register map and further information, see the AMD Am79C973/Am79C975 PCnet-Fast III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY product manual. The URL for the AMD website is http://www.amd.com. 5-5. Intel 21554 Register Map For more information, see the Intel 21554 PCI-to-PCI Bridge for Embedded Applications Hardware Reference Manual. The URL for Intel’s website is http://www.intel.com. 5-6.
5-7.
Interrupt Source Register (ISR) The ISR is a 16-bit read-only register that is accessible by the MPC8245. The 16 interrupts are latched into this register and cleared when the interrupt has been deasserted. ISRA Interrupts. Table 5-7 shows the interrupts assigned to ISRA. Table 5-7 Interrupt Source Register A – FFE20000 Bit 7–4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved INT11 INT10 INT9 INT8 Note: When any of the bits is a “1”, the corresponding interrupt is asserted.
Interrupt Enable Register A (IERA) The Interrupt Enable Register A (IERA) contains an interrupt enable mask. The device interrupt status appears in the interrupt source registers. Setting a “1” to any of the bits enables the corresponding interrupt Table 5-9 shows the interrupts assigned to the IERA.
Board Status Register (BSR) The BSR controls two board status LEDs on the panel. It also controls the Power LED. Table 5-11 shows the functions assigned to the BSR bits.
LED Registers (LED) On power up, all LEDs will be off until the LED bits are set to a 1. See Section 4-4, LEDs, for complete definitions of each LED. Writing a “1” to any LED bit turns on the corresponding LED. Table 5-12 shows the bits assigned to the LED register.
Port Option Register (POR) The Port Option Register (POR) is a read-only register. This register indicates the number and type of ports in the product specific design. Table 5-14 shows the bits assigned to the POR.
Board Option Register (BOR) The Board Option Register (BOR) is a read-only register. This register indicates the configuration and product type. Table 5-15 shows the bits assigned to the BOR.
General Purpose Register (GPR) The General Purpose Register (GPR) is a read/write register. Bits 0 and 1 are not used. Table 5-16 shows the functions assigned to the GPR bits.
Programming Information HW400p/M Technical Reference - 1.
