HighWire HW400c/2 User Reference Guide Rev 1.0 ___________________HighWire HW400c/2 User Reference Guide M8275, Rev 1.0 October 10, 2006 Copyright 2006, SBE, Inc.
HighWire HW400c/2 User Reference Guide Rev 1.0 Copyright ©2006 by SBE, Inc. All rights reserved. No part of this manual may be reproduced by any means without written permission from SBE, Inc., except that the purchaser may copy necessary portions for internal use only. While every effort has been made to ensure the accuracy of this manual, SBE cannot be held responsible for damage resulting from information herein. All specifications are subject to change without notice. SBE, Inc.
HighWire HW400c/2 User Reference Guide Rev 1.0 Revision History Revision 1.0 October 10, 2006 Date Changes October 10, 2006 Initial Release Copyright 2006, SBE, Inc.
HighWire HW400c/2 User Reference Guide Rev 1.0 THIS PAGE IS INTENTIONALLY LEFT BLANK October 10, 2006 Copyright 2006, SBE, Inc.
HighWire HW400c/2 User Reference Guide Rev 1.0 Table of Contents Revision History............................................................................................................................iii Table of Contents .......................................................................................................................... v List of Figures ...............................................................................................................................
HighWire HW400c/2 User Reference Guide Rev 1.0 3.2 MV64462 System Controller .............................................................................................. 17 3.2.1 System Bus ................................................................................................................ 17 3.2.2 Dual Data Rate (DDR) SDRAM ............................................................................... 17 3.2.3 Host PCI Bus .....................................................................
HighWire HW400c/2 User Reference Guide Rev 1.0 3.6.7 IPMI System Power Supply ...................................................................................... 42 3.6.8 IPMI Firmware EEPROMs ....................................................................................... 42 3.6.9 Zircon PM Reset........................................................................................................ 43 3.6.10 IMPI Get Device ID ......................................................................
HighWire HW400c/2 User Reference Guide Rev 1.0 4.4.3 Reading BCM5388 Register...................................................................................... 65 4.4.4 Writing a BCM5388 Register.................................................................................... 65 5 Linux on the HW400c/2 and Host system................................................................................. 67 5.1 Host Hardware and Software Requirements ........................................................
HighWire HW400c/2 User Reference Guide Rev 1.0 List of Figures Figure 1. HW400c/2 Block Diagram ........................................................................................................... 3 Figure 2. The HW400c/2 PTMC Processing Platform ................................................................................ 8 Figure 3. HW400c/2 Front Panel ................................................................................................................. 9 Figure 4.
HighWire HW400c/2 User Reference Guide Rev 1.0 Table 14. Layer 2 Switch Port Assignments.............................................................................................. 27 Table 15. Compact PCI connector J3 pin out ............................................................................................. 30 Table 16. Mezzanine Card Power Budget ................................................................................................. 33 Table 17. PTMC/PMC Connector Summary ..........
HighWire HW400c/2 User Reference Guide Rev 1.0 Table 48. Warm Reset Register (WRR) Offset address 0x17..................................................................... 58 Table 49. SPI Page Register (SPR) Offset Address 0x1A ......................................................................... 58 Table 50. SPI Address Register (SAR) Offset Address 0x1B ................................................................... 58 Table 51. SPI Read Byte Offset Select Register (SOR) Offset Address 0x1C......
HighWire HW400c/2 User Reference Guide Rev 1.0 Conventions The following conventions are used in this document: A # following a signal name, e.g., INTA#, represents an active low signal. A / preceding a signal name, e.g., /INTA represents an active low signal. 0x preceding a number represents a Hexadecimal value. A number in “ ” preceded by H represents a Hexadecimal value. A number in “ ” preceded by B represents a Binary value.
HighWire HW400c/2 User Reference Guide Rev 1.0 1 ABOUT THIS MANUAL This manual is technical reference for the HighWire HW400c/2 Gigabit Switched PTMC Processing Platform for CompactPCI. This manual is intended for those who are installing the HW400c/2 into a system.
HighWire HW400c/2 User Reference Guide Rev 1.0 2 INTRODUCTION The HW400c/2 is a flexible high-performance core processing platform for building powerful processor enabled CompactPCI (CPCI) telephony and data communications I/O solutions. Advanced features on the HW400c/2 include two PCI Telecom Mezzanine Card (PTMC) sites for CT Bus enabled I/O interfaces that are interconnected through a high-speed Layer 2 Gigabit Ethernet switch to the dual node CompactPCI Packet Switched Backplane (cPSB).
HighWire HW400c/2 User Reference Guide Rev 1.0 Processor Motorola MPC7447A SDRAM PTMC Site A PTMC Site B Config #2 or #5 Config #2 or #5 SDRAM I2C Config. ROM System Controller Discovery III Console RJ45 Enet MAC CPLD PCI-X TDM GigE or Rear I/O PCI-X TDM GigE or Rear I/O Microwire Serial EEPROM Boot ROM Phy Phy SRAM Disk on Chip Enet RJ45 Temp Temp Sensors Sensors Layer 2 Ethernet Switch 10/100/ 1000 Phy Flash Flash Memor Memory H.
HighWire HW400c/2 User Reference Guide Rev 1.0 2.3 Handling Procedures The HW400c/2 board uses CMOS components that can be easily damaged by static electrical discharge. To avoid damage, familiarize yourself with electrostatic discharge (ESD) procedures, which include the following precautions: • The board should be handled only by trained service personnel at an approved ESD workstation. • Refer to ANSI/IPC-A-610 developed by the Institute for Interconnecting and Packaging Electronic Circuits (IPC).
HighWire HW400c/2 User Reference Guide Rev 1.0 2.5 Returns/Service Before returning any equipment for service, you must obtain a Return Material Authorization (RMA) number from SBE: TEL: 800-925-2666 (Toll free, USA) TEL: +925-355-2000 (Outside of USA) FAX: +925-355-2020 Ship all returns to SBE’s USA service center: SBE, Inc. 4000 Executive Parkway, Suite 200 San Ramon, CA 94583 SBE’s Technical Support Department can be reached at 800-444-0990. 2.
HighWire HW400c/2 User Reference Guide Rev 1.0 2.7 Mean Time Between Failures (MTBF) The Mean Time Between Failure (MTBF) of SBE, Inc’s HW400c/2 was calculated per Telcordia Technical Reference TR-332 Issue 6, December 1997. The following specific parameters were used: Prediction method: Application conditions: Environment: Component quality factors: Ambient temperature: Method I (Parts count procedure) Case 1 (<1 hr burn-in, 50% electrical stress) Controlled, fixed, ground (mult. factor = 1.
HighWire HW400c/2 User Reference Guide Rev 1.0 2.8 Regulatory Agency Certifications The HW400c/2 complies with the requirements listed below. 2.8.1 Safety • • • • IEC60950 International product safety IEC60950 UL60950 Certified Body (CB) Report pending pending pending pending 2.8.2 US and Canadian Emissions • • FCC Part 15 Class B Industry Canada CS-003 pending pending 2.8.
HighWire HW400c/2 User Reference Guide Rev 1.0 2.10 Physical Properties The Highwire 400c/2 is compliant with the mechanical specifications of PCMIG 2.0. Table 2 lists the physical dimensions of the HW400c/2 product. Figure 2 shows the physical profile of the HW400c/2 board. Table 2. HW400c/2 Physical Dimensions Length: Width: Maximum component height (front): Maximum component height (back): Board thickness: 9.2 inches (233.68 mm) 6.3 inches (160.02 mm) 0.540 inches (13.72 mm) 0.079 inches (2 mm) 0.
HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.1 HW400c/2 Front Panel The HW400c/2 CompactPCI front panel has custom cut outs with the appropriate thickness to accommodate two PTMC bezels (with EMC gaskets), two RJ-45 connectors, blue Hot Swap LED, green power LED, and status LEDs. Figure 3 below shows an illustration of the front panel. Figure 3. HW400c/2 Front Panel October 10, 2006 Copyright 2006, SBE, Inc.
HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.2 Part number and serial number All boards are marked with the manufacturing part number and assembly revision. This is marked on a label and affixed to the top of the board. All boards are serialized physically with a bar code serial number label and affixed to the secondary side of the board. 2.10.3 Bus Keying Keying on the HW400c/2 is used to prevent damage to the card and/or the backplane.
HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.4 Power Requirements The power requirements of the HW400c/2 are defined for two environments: • CompactPCI VIO of 5.0v (see Table 3) • CompactPCI VIO set 3.3v (see Table 4). 1. All voltages are required. 2. The CompactPCI VIO has no effect on the local PCI bus VIO (PTMC sites), which is fixed at 3.3v. Table 3. HW400c/2 power requirements VIO = 5.0V 3.3V 5.
HighWire HW400c/2 User Reference Guide Rev 1.0 2.10.5 Switches The HW400c/2 contains single switch that is necessary for normal operation. The switch is an integral part of the lower ejector handle inside the front panel, and is used along with the blue LED (see Figure 3) and the Linear Systems LTC1644, for hot swap. The switch is connected to the PC board at J10 near the lower ejector handle. For debugging purposes an optional reset/NMI toggle switch and cable is available (see Section 3.1.3).
HighWire HW400c/2 User Reference Guide Rev 1.0 3 FUNCTIONAL BLOCKS The HW400c/2 has six major functional blocks – the PowerPC processor, system controller, CT Bus interface, Ethernet switch, PTMC expansion sites, and the IPMI controller. The following sections describe these functional blocks in greater detail. Additional features such as the connector pin outs and JTAG development support are also described. 3.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.1.2 Console port The front panel console port is connected through the MV64462 via a Linear Systems LTC1386 EIA-562 (low voltage EIA-232) transceiver. The console port is an RJ45 modular connector mounted on the front panel using three wire (Tx, Rx, GND) EIA232 at 9600 baud, 8N1 (8 bits, No parity, 1 stop bit). Figure 4 shows the console port pin out. Pin 1 1 2 3 4 5 6 7 8 n/c n/c Tx Rx CONSOLE Shield Figure 4. Console port pin out 3.1.
HighWire HW400c/2 User Reference Guide Rev 1.0 Table 7 describes the pin out of J8 and J9. Some of the pins listed are for Factory use only. Table 7. J8 and J9 pin out Header J8 J9 Pin 1 2 3 4 5 Label O SCL none SDA NMI 6 1 (-) O 2 3 none none 4 I2C2 5 RST 6 I2C2 Usage N/C. The “o” indicates pin one TWSI IPMB SCL, for Factory use only N/C. Just below the “J8” header title. TWSI IPMB SDA, for Factory use only Ground.
HighWire HW400c/2 User Reference Guide Rev 1.0 Figure 7. Optional Reset/NMI switch 3.1.4 COP/JTAG Port A 16-pin header (J6, see Figure 2, and Figure 8) and a 6-pin header (JX6) are provided on the HW400c/2 board for connecting to the processor’s COP (Common On-chip Processor) port for factory development purposes. The J6 header can also be used to access the JTAG chain for the entire board. The COP/JTAG port uses 3.3V signaling. Figure 8. COP/JTAG Pinout 3.1.
HighWire HW400c/2 User Reference Guide Rev 1.0 Table 8. J7 pin functions 3.1.5.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.3 Host PCI Bus The Marvell Discovery III (MV64462) host PCI bus (PCI bus 0) provides an interface between the processor and CompactPCI host, as well as between the PTMC sites and the CompactPCI host. The MV64462 device acts as a PCI-to-PCI bridge between the two PCI buses. The HW400c/2 supports a 64-bit-wide bus operating at 33 or 66 MHz. PCI-X operation at 66 MHz is supported; however 100/133 MHz operation is not supported. 3.2.3.
HighWire HW400c/2 User Reference Guide Rev 1.0 If a PCI-X 133 card is installed in Site B, it may be forced to 100 MHz, by installing the LPCI jumper at J7 (see Section 3.1.5). Module presence is detected by the state of the BUSMODE1 pin. Interrupts from either of the two sites are fed through the MV64462 GPIO pins, and can be routed to either the on-board processor or through the host PCI bus to the CompactPCI host processor.
HighWire HW400c/2 User Reference Guide Rev 1.0 Table 9.
HighWire HW400c/2 User Reference Guide Rev 1.0 Table 10.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.6 MV64462 Ethernet Interface The MV64462 contains an Ethernet MAC, which provides a MAC-to-MAC connection to port 7 of the on-board Broadcom BMC5388 layer 2 Ethernet switch (see Table 14). The connection is made via the RGMII ports on each device. The operating speed of the RGMII port is 125 MHz. 3.2.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.7.4 CT Bus Controller The Agere T8110L CT bus controller on the HW400c/2 board is accessed and programmed via the device bus. It also has a data bus width of 16 bits. Burst reads/writes are not supported by the T8110L. See Section 3.3 for details about the CT Bus Controller functions. 3.2.7.5 CPLD The Complex Programmable Logic Device (CPLD) registers are also accessed via the device bus, using an 8-bit data bus width.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.2.10 Multi-Purpose Port (MPP) Usage The MV64462 Discovery III includes a 32-bit Multi-Purpose Port (MPP) that can be used for a variety of possible functions. The HW400c/2 board uses the MPP for the serial Console Port signals (front-panel RJ-45), REQ and GNT signals for the local PCI bus, I2C EEPROM activity indicator (used during boot*), and as a detector for the various on-board interrupt sources.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.3 Computer Telephony Bus Controller The HW400c/2 includes the Agere T8110L CT Bus Controller to control TDM bus switching between the backplane (CompactPCI J4 connector) and the local bus, which is connected to the JN3 connector on each of the two PTMC sites. 3.3.1 H.110 Interface (T8110L) The Agere T8110L is a H.110 CT Bus controller that provides a complete interface between the backplane H.
HighWire HW400c/2 User Reference Guide Rev 1.0 Figure 10. Local CT Bus Clocking Block Diagram Control for the local “A” and “B” bus drivers is provided by bits 4, 5, 6, and 7 in the Clock Select Register (CSR). Refer to Section 4.2.1 for further details. Figure 11 shows the implementation. Figure 11. Local CT Bus Clock Generation October 10, 2006 Copyright 2006, SBE, Inc.
HighWire HW400c/2 User Reference Guide Rev 1.0 The T8110L can be programmed such that its local frame reference (LREF [3:2]) inputs are used to generate all of the TDM bus clocks and syncs. The T8110L Local Clock Reference Inputs have been assigned to the PTMC JN3 H.110 clock pins as shown in Table 13. Table 13. LREF [3:2] Assignments LREF input LREF2 LREF3 Assigned to Clock PT_NETREF1 PT_NETREF2 3.3.3 Operation in Non-H.110 Backplane The default HW400c/2 configuration has the H.110 interface installed.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.4.1 Switch Registers Initialization and Monitoring The switch is initialized and its registers polled by utilizing its SPI bus interface. This interface is connected through the CPLD. For a description of how to access the SPI interface, please refer to Section 4.4. 3.4.2 MV64462 System Controller Ethernet Interface The Marvell MV64462 System Controller on the HW400c/2 can be accessed via the BCM5388 Ethernet switch.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.4.4 PT5MC Ethernet Ports Each of the two PT5MC sites on the HW400c/2 have two 10/100/1000 Mbps ports connected to the Ethernet switch. The signals conform to PICMG ECN 2.15-1.0001, using the first 24 pins of the respective JN4 connectors. The JN4 Ethernet connections are switched to the CompactPCI J3 connector using a FET switch specially designed for signals such as Gigabit Ethernet.
HighWire HW400c/2 User Reference Guide Rev 1.0 Table 15. Compact PCI connector J3 pin out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A +5.0v +5.0v N/C LED Clock N/C LED Data N/C +3.3v +3.3v +3.3v N/C N/C N/C GND LPb DB+ LPb DA+ LPa DB+ LPa DA+ GND B +5.
HighWire HW400c/2 User Reference Guide Rev 1.0 The Link/Activity/Speed LED indication is as follows: • solid green when the network link is up • blinking at 3 Hz for 10 Mb/s Tx or Rx; • blinking at 6 Hz for 100 Mb/s Tx or Rx; • blinking at 12 Hz for 1000 Mb/s Tx or Rx. An optional front panel 2-high LED is provided as a status indicator for the Ethernet ports. The optional LEDs are shown as LEDs C and D in Figure 3, and by default are not present.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.5 Mezzanine Card Sites The HW400c/2 board supports I/O expansion using either one or two industrystandard PTMC and/or PMC modules. This section provides technical details for these expansion sites. 3.5.1 PT5MC Type Mezzanine Cards The PT5MC mezzanine card support includes connection to the local PCI bus (32-bit, 33-133 MHz PCI or PCI-X), the local 32 TDM stream H.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.4 Mezzanine Card Power Each of the two mezzanine card sites on the HW400c/2 is allotted a portion of the total power budget for the board. For the standard version, the mezzanine power budget is 16.2 Watts for each slot, while the optional high-power version allows 26.4 Watts for each slot. The power budget is divided between the 3.3V, 5V, and 12V power rails as shown in Table 16. Table 16.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.6 PTMC Jn1 and Jn2 PCI Connectors Communication using the local PCI bus is done across two PTMC/PMC connectors, JN1 and JN2. Table 18 shows the 32-bit PCI connector pin assignment for JN1 and JN2 on the HW400c/2 as defined by the PMC specification IEEE P1386.1. Table 18.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.7 PTMC Jn3 CT Bus Connector Table 19 shows the PTMC Pn3 CT Bus connector pin assignment for the HW400c/2 for both Configuration #2 (PT2MC) and Configuration #5 (PT5MC). The signal definitions for Pn3 are per the PICMG 2.15 specification. Table 19.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.8 PTMC Jn4 LAN/User I/O Connector Table 20 (Site A) and Table 21 (Site B) show the PTMC Pn4 LAN and/or User I/O connector pin assignment for the HW400c/2 for both Configuration #2 (PT2MC User I/O only) and Configuration #5 (PT5MC LAN and User I/O). 3.5.8.1 PTMC Site A Jn4 This table shows the connections from PTMC Site A Jn4, to the Compact PCI connector J5 and, for PT5MC, the signals for the Ethernet ports, Link Ports A and B.
HighWire HW400c/2 User Reference Guide Rev 1.0 Table 20.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.8.2 PTMC Site B Pn4 This table shows the connections from PTMC Site B Jn4 to the Compact PCI connector J5 and, for PT5MC, the signals for the Ethernet ports, Link Ports A and B. LPa (Link Port A) and LPb (Link Port B) for PTMC Site A go to the Ethernet Switch ports 3 and 5 respectively. See Table 14. PT5MC cards with network connections through Pn4, must be transformer coupled or the link to the layer 2 switch will not be established. ! Table 21.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.5.9 PTMC Site Voltage Keying Voltage key posts are installed at each PTMC site in accordance with IEEE 1386. See Section 2.10.3. ! The HW400c/2 local PCI bus I/O voltage is 3.3 volts only. Therefore, PTMC and PMC modules with 5 volt only I/O signals cannot be used on the HW400c/2 board, and are prevented from being installed by a key post residing at each site. 3.
HighWire HW400c/2 User Reference Guide Rev 1.0 Figure 13. IPMI Block Diagram Table 22.
HighWire HW400c/2 User Reference Guide Rev 1.0 Table 23. Voltage Monitor A/D Port Assignments for IPMI Supply Voltage Monitor A/D Port 5-Volt 3.3-Volt 1.1-Volt (CPU core) 1.5-Volt (System controller core) 2.5-Volt (SDRAM) A2D1 A2D2 A2D3 A2D4 A2D5 Table 24. HW400c/2 Temperature Sensor Locations Device Location I2C Port 1 Address TS0 (U84) MV64462 System Controller 0 TS1 (U83) CPU Internal Temperature 1 3.6.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.6.6 Board Reset via IPMI The IPMI controller has the capability to issue a board reset. A GPIO port on the Zircon PM (see Table 22) is connected to the CPLD and OR’ed with the /P_RST reset signal from the Host CompactPCI bus. A standard IPMI command is issued to initiate the board reset. IPMI commands are issued through an IPMI Shelf Manager 3.6.7 IPMI System Power Supply The Vsm supply pin on the CompactPCI J1 connector delivers 5V to the IPMI circuit.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.6.9 Zircon PM Reset At power-up, the Zircon PM is held in reset state until the 3.3V supply voltage is within tolerance. 3.6.10 IMPI Get Device ID The response to the IPMI command “GetDeviceID” from the Shelf Manager is of the standard format. See Appendix A for the complete response format to GetDeviceID.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.7 Hot Swap Support The HW400c/2 complies with the PICMG 2.1 specification for full hot swap in CompactPCI systems as defined by the PICMG 2.1 R2.0 specification. Hot swap functions, such as power FET control, are provided by a Linear Technologies LTC1664 Hot Swap Controller. 3.7.1 Hot Swap on J1 and J2 All signals to and from the CompactPCI backplane connectors J1 and J2 are precharged to a voltage of 1.0V. This voltage is derived from the 3.
HighWire HW400c/2 User Reference Guide Rev 1.0 3.7.5 Hot Swap Sequence The hot swap sequence is a coordination between the operator, the hardware on the HW400c/2 board, and the host system board that is capable of basic, full, or highavailability hot swap. Table 27 outlays the Hot Swap insertion and extraction sequences. Table 27. Overview of Hot Swap Insertion/Extraction Sequences Sequence Type Sequence Process INSERTION When the board is inserted into the enclosure, the following occurs: 1.
HighWire HW400c/2 User Reference Guide Rev 1.0 4 PROGRAMMING INFORMATION The HW400c/2 memory map and programmable register information is provided in this section. 4.1 HW400c/2 Memory Map Table 28 shows the memory map for the HW400c/2 board. Table 28. HW400c/2 Memory Map Address Start (Hex) Address End (Hex) Device Device No.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2 CPLD Registers All CPLD (Complex Programmable Logic Device) registers are 8-bit registers that are accessible by the system controller. 1: All reserved locations and bits are set to zero after a reset to the CPLD. 2: Check individual register descriptions for default register values after reset. Table 29.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.1 Clock Select Register (CSR) The Clock Select Register (CSR) is a Read/Write register. This register selects whether or not the H.110 Controller (T8110L) drives the H.110 and local CT bus sync and clock. The register bit definitions are shown in Table 30. Table 30. Clock Select Register (CSR) Offset Address 0x04 Bit 7 L_N2SRC Bit 6 L_N1SRC Bit 5 L_C8ASRC Bit 4 L_C8BSRC Bit 3 H_C8ASRC Bit 2 H_C8BSRC Bit 1 Bit 0 Reserved Reserved The backplane H.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.2 Board Status Register (BSR) The Board Status Register (BSR) is a Read/Write register. This register reflects the presence of the CT bus (H.110, see Section 3.3.3), the state of the FACT (Factory) jumper in J7 (see Figure 9), and can control and report the state of two of the status LEDS on the front panel (see Figure 3). Table 31.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.4 Memory Option Register (MOR) The Memory Option Register (MOR) is a Read-Only register. This register reports the presence and size of the M-Systems Disk on Chip device. Table 33.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.6 PTMC Reset Register (PRR) PTMC Reset Register (PRR) is a Read/Write register that asserts and de-asserts reset to the individual PTMC sites. The Reset pulse applied to the PTMC modules must conform to the PCI standard, that is, it must be at least 10 PCI clock cycles long. Table 35.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.8 Board Option Register (BOR) The Board Option Register (BOR) is a Read Only register. This register indicates the configuration and product type. Bit 5, bit 2, bit 1 and bit 0 are always “1” for the HW400c/2 board. Table 37.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.10 PCI Status Register (PSR) The PCI Status Register (PSR) is a Read-Only register and indicates the status of the host and local PCI buses. The bits of this register are defined as follows. Table 39.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.12 Hardware Revision Register (HRR) The Hardware Revision Register (HRR) is a Read-Only register. It contains the current major and minor (optional) hardware revision for the board. Table 41. Hardware Revision Register (HRR) Offset Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HRR7 HRR6 HRR5 HRR4 HRR3 HRR2 HRR1 HRR0 HRR[7:4] = xxxx HW400c/2 Major Revision HRR[3:0] = yyyy HW400c/2 Minor Revision 4.2.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.14 PLL Configuration Register B (PLLB) The PLL Configuration Register B (PLLB) is a Read-Only register. It contains the settings for the System bus and Device bus (external) PLLs. Reading this register (along with PLLA) can help software determine the CPU operating frequency, as well as the Device bus operating frequency. Table 43.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.15 LED Register B (LEDB) The LED Register B (LEDB) is a Read/Write register. It contains controls for the eight on-board surface-mount LEDs as well as the optional LAN status LEDs. Table 44.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.16 Device Control Register (DCR) The Device Control Register (DCR) is a Read/Write register, which controls the CPU timer enable and three resets. The Reset pulse applied to any device must conform to the specifications of that particular device. Please refer to the applicable device manual for details. Table 46.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.18 Warm Reset Register (WRR) The Warm Reset Register is a Read/Write Register. Writing a value of 0x77 to the Warm Reset Register initializes a Warm Reset. The actual reset signal is driven by the CPLD 1-2 milliseconds after writing 0x77 to the WRR. The CPU, System Controller, CPLD registers, T8110, Disk on Chip, Ethernet Switch and PHYs, and local PCI (PCI1) are all reset. Host PCI (PCI0) reset is not affected.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.21 SPI Read Byte Offset Register (SOR) The SPI Byte Offset Select Register is a Read/Write register. It is used for selecting the desired byte offset (within the register selected by the SAR) when reading from the BCM5388 Ethernet Switch SPI port. In the case where the entire register is not being read, the SOR can be set to a non-zero value to index to the desired starting byte. Table 51.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.23 Write Byte Count Register (WBC) The Write Byte Count Register is a Read/Write register. It is used for setting the number of bytes to be written when writing to the BCM5388 SPI port. All bytes in a given register must be written; for example, if the register to be written contains 3 bytes, then WBC[3:0] must be set to 0011. When this register is written, the internal SPI Write State Machine is initiated.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.25 SPI Error and Status Register (SESR) The SPI Error Register is a Read Only register. SBSY clears when the previous operation is completed, and the SPIFER, RACKER, and BYTER error flags clear when the next operation is started. SBSY can be polled immediately after writing to the RBC or WBC registers. SPIFER, RACKER and BYTER are valid after SBSY=0 (Interface Ready), but are cleared when writing to the RBC or WBC registers for the next operation.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.27 EEPROM Operation/Status Register (EOSR) The EEPROM Operation and Status Register is a Read/Write register. It is used for initiating a read or write operation to the EEPROM, and checking the programming status after a write operation. Bits 0-3 are self-clearing, and bit 7 clears when the next operation is started. Attempting to write EEPROM word addresses 0x00-0x0F without the FAC jumper installed results in a write error, setting WERR bit.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.2.28 EEPROM Data Registers (EDR0 – EDR1) The EEPROM Data Registers are Read/Write registers. They are used for holding data bytes to be read from or written to the serial EEPROM. Values written to EDR0-1 are stored in an internal shift register and cannot be read back by reading EDR0-1. They are written to the EEPROM during a write operation. Reading EDR0-1 returns serial data obtained from the most recent EEPROM ERD operation.
HighWire HW400c/2 User Reference Guide Rev 1.0 4.3.2 Writing an EEPROM Address A. Check the EBSY flag in the EEPROM Operation/Status Register (EOSR, see Section 4.2.26). If set to “0”, proceed to the next step. B. Write a “0x01” to the EOSR. This starts the Write Enable operation (EWEN). C. Check the EBSY flag. If set to “0”, EWEN is complete – proceed to the next step. D. Set the EEPROM Address Register (EAR, see Section 4.2.25) to the desired word address. E.
HighWire HW400c/2 User Reference Guide Rev 1.0 RBC to a size that exceeds the actual register size will result in an incorrect read value. No error flags will be set to indicate these types of errors. ! When reading or writing the BCM5388 registers, ensure that the register size values are in strict accordance with the BCM5388 data sheet. 4.4.3 Reading BCM5388 Register A. Check the SBSY flag in the SPI Error and Status Register, bit 0 (SESR, see Section 4.2.24). If set to “0”, proceed to the next step.
HighWire HW400c/2 User Reference Guide Rev 1.0 D. Write the bytes to be written into the SPI Data Registers (SDR0-7, see Section 4.2.24), beginning with LSB in SDR0. E. Set the Write Byte Count Register (WBC, see Section 4.2.23) to the count of bytes to write. This step initiates writing to the Ethernet switch. ! The register will not be written if this count differs from the size of the Ethernet switch register. There are no error flags to indicate this type of error. F.
HighWire HW400c/2 User Reference Guide Rev 1.0 5 LINUX ON THE HW400C/2 AND HOST SYSTEM The HW400c/2 uses an off the shelf 2.6.9 PPC Linux kernel distribution from Gentoo (www.gentoo.org) with some additional files added specific to the HW400c/2, and with the GenericHDLC WAN stack enabled. The Gentoo Linux kernel may be delivered as a generic compressed archive that can be downloaded, or on a CD-ROM available from SBE. The compressed image is the tar gzip (.
HighWire HW400c/2 User Reference Guide Rev 1.0 • Recent distribution of Linux installed. Because Gentoo Linux is based on the 2.6 series Linux kernel, it is best to use Gentoo Linux in conjunction with a host that has a Linux distribution based on the 2.6 kernel. 5.2 Network and System Configuration Booting Linux on the HW400c/2 requires services that are traditionally installed as part of a server or development Linux installation.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.4 Configuring the Host System The next few sections describe daemons and system services that must be installed and correctly activated in order to boot the Linux kernel on the HW400c/2 and subsequently compile applications for the HW400c/2. 5.4.1 Modifying the Host Path Since all software is compiled natively on the HW400c/2, there is no need to modify the host’s path. 5.4.
HighWire HW400c/2 User Reference Guide Rev 1.0 The parenthesized access privilege values shown in the previous example should be sufficient. These access privileges specify that the target system at the specified IP address will have read/write access to the exported file system, and that the user ID (UID) of the root user on the target system will not be prevented from writing or modifying files in the NFS mounted file system.
HighWire HW400c/2 User Reference Guide Rev 1.0 text editor to remove the hash mark on each line that contains the string tftp. Active TFTP entries in /etc/services should look like the following: tftp 69/tcp tftp 69/udp Depending on the Linux distribution and version you are using on the host, Linux systems typically use one of two mechanisms to activate and manage network servers such as TFTP servers. These are the Extended Internet Services Daemon, xinetd, and the older Internet Services Dameon, inetd.
HighWire HW400c/2 User Reference Guide Rev 1.0 # ps alxww | grep inet 140 0 578 1 0 0 1152 356 do_select S ? 0:00 inetd 0 500 13361 13336 18 0 1360 508 pipe_read S ? 0:00 grep -i inet The alxww options to ps cause the command to display all system processes in an extremely wide listing. The grep then searches for the string inet in the resulting output.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.4.5 Configuring tftp with xinetd The servers that can be managed by the xinetd are each listed in a server-specific configuration file located in the directory /etc/xinetd.d. The file for the TFTP server is aptly named tftp, and looks like the following: # # # # # default: off description: The tftp server serves files using the Trivial File Transfer \ Protocol.
HighWire HW400c/2 User Reference Guide Rev 1.0 This command will stop and then start all of the Internet services on your Linux system. You may not want to do this if your system is running Internet services on which other systems depend, as it will cause a slight interruption in those services.
HighWire HW400c/2 User Reference Guide Rev 1.0 If you don’t already have one, the easiest way to create a bootp server is to have it reside on the same LAN subnet as the HW400c/2. Creating bootp relay agents for bootp servers on different LAN segments is beyond the scope of this document. To set up a server with BOOTP with TFTP ability in a standard Linux box, uncomment (or add) these two lines in inetd.conf) tftp bootps dgram dgram udp udp wait wait root root /usr/sbin/tcpd /usr/sbin/tcpd in.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.1 U-boot, Universal Bootloader The HW400c/2 uses a boot ROM based on Das U-boot. U-boot (Universal Bootloader) is an off-the-shelf freeware package found on Sourceforge.net. Many commands and environment variables are available in U-boot to facilitate the loading of the Linux kernel from various locations. 5.5.1.1 U-boot commands There are four basic U-boot commands that are used to configure the environment variables for the boot environment.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.1.2 U-boot environment variables U-boot has large number of environment variables and commands. While most can be used with the HW400c/2, only a few are necessary for the boot process. A complete list of U-boot environment variables can be found in Appendix B . List of basic boot variables: bootargs Boot arguments. Arguments passed to the kernel.
HighWire HW400c/2 User Reference Guide Rev 1.0 keystroke will stop the countdown and drop into the U-boot debug shell. baudrate Baud rate of the HW400c/2 console (debug) port ethaddr This unit’s MAC address. The MAC address is assigned by SBE at the time of manufacture, stored in non-volatile memory, and must not be altered. Any attempt to change the MAC address will be ignored. ipaddr This unit’s static IP address (if used) in dot notation. If not used, should be set to 0.0.0.0 for clarification.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.1.3 Power up call trace For reference purposes, this is a summary of the power up calls after U-boot runs and jumps to _start. _start (…/arch/ppc/kernel/head.S) early_init (…/arch/ppc/kernel/setup.c) start_here (…/arch/ppc/kernel/head.S) machine_init (…/arch/ppc/kernel/setup.c) platform_init (…/arch/ppc/platforms/gigateak.c) start_kernel (…/init/main.c) setup_arch (…/arch/ppc/kernel/setup.c) gigateak_setup_arch (…/arch/ppc/platforms/gigateak.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.2 Booting with tftp Tftp boot requires a tftp boot server and an NFS mounted file system. If a static IP address is not assigned to the HW400c/2 through the boot console, a bootp server may also be necessary. The bootp server, tftp server, and the NFS server functions may or may not be the same machine. 5.5.2.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.2.2 U-boot parameters for tftp with static IP address The following example shows U-boot parameters necessary for a tftp download and boot with a static IP address assigned using the U-boot command: # set ipaddr Using this method, the gateway IP address (gatewayip), the tftp server IP address (serverip), netmask (netmask), and boot file name (bootfile) must also be assigned using the u-boot command set.
HighWire HW400c/2 User Reference Guide Rev 1.0 TFTP from server 10.0.0.5; our IP address is 10.0.0.10 Filename 'uImage'. Load address: 0x400000 Loading: ################################################# ################################################# ################################################# ################################################# ############################### done Bytes transferred = 1551015 (17aaa7 hex) ## Booting image at 00400000 ... Image Name: Linux-2.6.
HighWire HW400c/2 User Reference Guide Rev 1.0 HDLC support module revision 1.17 Cronyx Ltd, Synchronous PPP and CISCO HDLC (c) 1994 Linux port (c) 1998 Building Number Three Ltd & Jan "Yenya" Kasprzak. Loading Adaptec I2O RAID: Version 2.4 Build 5go Detecting Adaptec I2O RAID controllers... megaraid cmm: 2.20.2.0 (Release Date: Thu Aug 19 09:58:33 EDT 2004) megaraid: 2.20.4.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.3 Booting with Disk on Chip A Disk-on-Chip (DoC) flash file system device is used on the HW400c/2 for data storage. DoC is a high-density flash device manufactured by M-Systems Incorporated, and has a data bus width of 16 bits. The 128 MB device is standard on the HW400c/2, with the option of populating other devices for OEM configurations.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.5.3.2 Creating a uRamdisk Image uRamdisk is a tiny kernel image needed to boot uImage from the Disk on Chip. uRamdisk has the same intent as a ramdisk on other linux platforms. It brings up necessary drivers needed to access the real kernel image (uImage). After booting the HW400c/2, the following commands will create uRamdisk. # dd if=/dev/zero of=ramdisk.image bs=1024 count=32768 # /sbin/mkfs.ext2 ramdisk.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.6 Compiling the Kernel (uImage) Unlike other some other Linux distributions, the Gentoo kernel can be natively compiled on the HW400c/2 following standard Linux kernel build procedures. Rebuilding the kernel is necessary when changing the kernel configuration parameters. These are the basic steps necessary to compile the kernel natively on the HW400c/2; 1. As root, change to the kernel source directory # cd /usr/src/linux-2.6.9-gigateak 2.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.6.1 Gentoo Application Packages Management “Portage” is the name of Gentoo's package management system. All Gentoo packages can be found under /usr/portage. If a package is needed, for example, firewall or ftp services, it can be found in the portage directory. Some of the package names are a bit obscure (for example, ssh is found under net-misc, while xinetd is found under sys-apps), so some research may be necessary to locate the needed package.
HighWire HW400c/2 User Reference Guide Rev 1.0 5.6.1.2 Enable remote login with ssh Gentoo Linux installs sshd by default, but it is not enabled. Before starting up an ssh server look through the configuration file at /etc/ssh/sshd_config. One thing that you should consider setting is PermitRootLogin no. This disables logins as root, which means that in order to log in, an attacker first must login as a regular user (in the wheel group) and then su.
HighWire HW400c/2 User Reference Guide Rev 1.0 # rc-update add vsftpd default You may also want to modify your /etc/vsftpd/vsftpd.conf file configuration and security parameters. Some of the basic parameters in /etc/vsftpd/vsftpd.conf can be: dirmessage_enable=YES # banner_file=/etc/vsftpd/vsftpd.
HighWire HW400c/2 User Reference Guide Rev 1.0 Appendix A IPMI GetDeviceID Response message data to IPMI GetDeviceID request. Values in bold are changes from default Zircon firmware response message.
HighWire HW400c/2 User Reference Guide Rev 1.0 Appendix B U-Boot Environment variables Das U-boot was created by Wolfgang Denk as an open source boot and debug firmware. A complete U-boot manual can be found at http://www.denx.de/wiki/bin/view/DULG/Manual. This appendix is a brief list of known U-boot environment variables accessed by entering the command help or ? at the debug prompt. Note: Some commands may not work on the SBE HW400c/2.
HighWire HW400c/2 User Reference Guide Rev 1.
